Publications - Ran Ginosar

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Last Update:21/01/14

Book:

Y. Perelman and R. Ginosar, The NeuroProcessor: An Integrated Interface to Biological Neural Networks, Springer, 2008.

Many-Core Architecture:

  1. R. Ginosar and D. Egozi, "Topological Comparison of Perfect Shuffle and Hypercube," Int. J. Parallel Programming, 18(1):37-68, 1989.

  2. L. Yavits, Architecture and design of an associative processor chip for image processing and computer vision, MSc thesis, EE, Technion, 1994.

  3. Bayer, N. and R. Ginosar, "Tightly Coupled Multiprocessing: The Super Processor Architecture," in Q. Jin, J. Li, N. Zhang, J. Cheng, C. Yu and S. Noguchi (ed.), "Enabling Society with Information Technology," Springer, pp. 329-339, 2002.

  4. R. Ginosar, Many-cores: Supercomputer-on-chip, presentation at the Israel CMP Day III, 3 Feb 2009.

  5. D. Khoretz, E. Friedman and R. Ginosar, “HyperCoreX: Non-Equidistant Memory Network in a Many-core Architecture,” Technical Report, 2011.

  6. I. Avron and R. Ginosar, “Performance of a Hardware Scheduler for Many-core Architecture,” HPCC-ICESS 2012, pp. 151-160.

  7. A. Morad, T. Morad, L. Yavits, R. Ginosar and U. Weiser, "Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC," Computer Architecture Letters, 2012.

  8. L. Yavits, A. Morad, R. Ginosar, "Cache Hierarchy Optimization,” Computer Architecture Letters, 2013.

  9. R. Ginosar, “The Plural Architecture: Shared Memory Many-cores with Hardware Scheduling,” IEEE 7th Int. Symp. On Embedded Multicore/Manycore SoCs (MCSoC), Tokyo, Japan, Sept. 2013 (invited keynote speech).

  10. R. Ginosar, “Mathematical modeling of many-cores,” Shonan workshop on Many-Cores and On-Chip Interconnects, Shonan Village Center, Japan, Sept. 2013.

  11. L. Yavits, A. Morad and R. Ginosar, “3D Cache Hierarchy Optimization,” 3DIC conference, San Francisco, USA, Oct. 2013.

  12. L. Yavits, A. Morad, R. Ginosar, “The Effect of Communication and Synchronization on Amdahl's Law in Multicore Systems,” accepted for publication, Journal of Parallel Computing, 2013.

  13. L. Yavits, A. Morad, R. Ginosar, “Computer Architecture with Associative Processor Replacing Last Level Cache and SIMD Accelerator,” accepted for publication, IEEE Trans. On Computers, 2013.

  14. A. Morad, T. Morad, L. Yavits and R. Ginosar, “Optimization of Asymmetric and Heterogeneous MultiCore,” 2013.

  15. L. Yavits, A. Morad, R. Ginosar and E.G. Friedman, “Associative Processor Thermally Enables 3-D Integration of Processing and Memory,” 2013.

  16. L. Yavits, A. Morad and R. Ginosar, “Sparse Matrix Multiplication on an Associative Processor," 2013.
  17. A. Morad, L. Yavits and R. Ginosar, "Convex Optimization of Resource Allocation in Asymmetric and Heterogeneous MultiCores," 2014.

VLSI Architecture for Brain-Machine Interface:

  1. Y. Perelman and R. Ginosar, “Analog Front-end IC for Multi-channel Neuronal Recording System with Spike and LFP Separation,” Journal of Neuroscience Methods 153 (2006) 21–26.

  2. Y. Perelman and R. Ginosar, “An Integrated System for Multichannel Neuronal Recording with Spike / LFP Separation and Digital Output,”  2nd Int. IEEE EMBS Conf. Neural Engineering, 2005, pp. 377-380.

  3. A. Zviagintsev, Y. Perelman and R. Ginosar, “Low-Power Architectures for Spike Sorting,” 2nd Int. IEEE EMBS Conf. Neural Engineering, 2005, pp. 162-165.

  4. A. Zviagintsev, Y. Perelman and R. Ginosar, “A Low-Power Spike Detection and Alignment Algorithm,” 2nd Int. IEEE EMBS Conf. Neural Engineering, 2005, pp. 317-320.

  5. A.Lyakhov, Y. Perelman, S. Marom and R. Ginosar, “Neurons on a Chip,” one page poster, 2005.

  6. Y. Perelman and R. Ginosar, "A Low Power Inverted Ladder D/A Converter," to be published, IEEE Trans. on Circuits and Systems II, 2006.

  7. Y. Perelman and R. Ginosar, “An Integrated System for Multichannel Neuronal Recording with Spike / LFP Separation, Integrated A/D Conversion and Threshold Detection,” IEEE Trans. on Biomedical Engineering, 54(1):130-137, 2007.

  8. A. Zviagintsev, Y. Perelman and R. Ginosar, “Algorithms and Architectures for Low Power Spike Detection and Alignment," Journal of Neural Engineering, 3:35-42, 2006.

  9. A. Zviagintsev, Y. Perelman and R. Ginosar, “Algorithms and Architectures for Low Power Spike Sorting," 2005.

  10. A.Lyakhov, Y. Perelman, S. Marom and R. Ginosar, “Low cost CMOS multi-electrode arrays,” 5th Int. Mtg on Substrate-Integrated Micro Electrode Arrays (MEA), Germany, July 2006.

  11. Z. Yekutieli, Y. Perelman, R. Ginosar and S. Marom, A Multichannel Recording Frontend for MEA, 5th Int. Mtg on Substrate-Integrated Micro Electrode Arrays (MEA), Germany, July 2006.

VLSI Architecture for Imaging:

  1. Adaptive Sensitity (see also VISL).

  2. O. Yadid-Pecht, R. Ginosar, and Y. Shacham-Diamand, “A Random Access Photodiode Array for Intelligent Image Capture,” IEEE Transactions on Electron Devices, 38(8), pp. 1772-1780, August 1991.

  3. S. Chen, R. Ginosar, “Adaptive Sensitivity CCD Image Sensor,” SPIE 2415: CCD and Solid Sate Optical Sensors V, San Jose, CA, Feb. 1995.

  4. R. Ginosar and S. Chen, “Adaptive Sensitivity TDI CCD Image Sensor,” EuroOpt / SPIE workshop on Advanced Focal Plane Arrays and Electronic Cameras, Germany, Oct. 1996.

  5. R. Ginosar and A. Gnusin, “Adaptive Sensitivity CMOS Image,” IEEE Workshop on CCD and Advanced Image Sensors, Belgium, June 1997.

  6. S. Wolf, R. Ginosar and Y.Y. Zeevi, "Spatio-Chromatic Image Enhancement Based on a Model of Human Visual Information Processing" , J. Visual Communication and Image Representation, 9(1), March 1998, pp. 25-37.

  7. M. Sherman and R. Ginosar, "Intelligent Scan", Israel IEEE Conf., 1995.

  8. H. Finkelstein and R. Ginosar, "Frontside bombarded metal-plated CMOS electron sensor", SPIE 3301: Solid State Sensor Arrays: Development and Applications II, Jan. 1998.

  9. U. Zangi and R. Ginosar,  "A Low Power Video Processor," Int. Symp. on Low Power Electronic Design, Monterey, CA, Aug. 1998.

  10. C. Friedman, A. Arbel and R. Ginosar, “The Current Skimming-Based CMOS Readout Architectures for Quantum Well Infrared Photodetectors,” 1999 IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, Kanagawa, Japan, June 1999.

  11. Perelman, Y. and R. Ginosar, “A Low-Light Level Sensor for Medical Diagnostic Applications,” IEEE Journal of Solid State Circuits, 36(10), pp. 1553-1558, Oct. 2001.

Asynchronous VLSI and clocking:

  1. I. David, R. Ginosar, and M. Yoeli, "An Efficient Implementation of Boolean Functions as Self-Timed Circuits,'' IEEE Trans. Computers, Jan. 1992.

  2. I. David, R. Ginosar, and M. Yoeli, "Implementing Sequential Machines as Self-Timed Circuits,'' IEEE Trans. Computers, Jan. 1992.

  3. David, I., Ginosar, R. and Yoeli, M., “Self-timed Architecture of a Reduced Instruction Set Computer,” Manchester Workshop on Asynchronous Logic, March 1993.

  4. I. David, R. Ginosar, and M. Yoeli, "Self-Timed is Self-Checking", Journal on Electronic Testing: Theory and Applications, 6, April 1995, pp. 219-228.

  5. R. Kol, R. Ginosar and G. Samuel, "Statechart Methodology for the Design, Validation, and Synthesis of Large Scale Asynchronous Systems",  IEICE Transactions, March 1997.

  6. R. Kol, "Self- Timed Asynchronous Architecture of an Advanced General Purpose Microprocessor," PhD Thesis, Sept. 1997.

  7. R. Kol and R. Ginosar,  "A Doubly-Latched Asynchronous Pipeline", IEEE International Conference on Computer Design (ICCD), Oct. 1997.

  8. WC. Chou, P.Beerel, R. Ginosar, R. Kol, C. Myers, S. Rotem, K. Stevens and K. Yun, "Average-case optimized technology mapping of one-hot domino circuits," ASYNC 1998

  9. R. Kol and R. Ginosar, "Adaptive Synchronization", IEEE International Conference on Computer Design (ICCD), Oct. 1998.

  10. R. Kol and R. Ginosar, KIN--An Asynchronous Processor, 12th ACM International Conference on Supercomputing (ICS’98), Jul. 1998.

  11. R. Kol, R. Ginosar and H. Shafi, Avid Execution on the Asynchronous Processor KIN, 3rd Euromicro Conference on Massively Parallel Computing Systems (MPCS’98), Apr. 1998.

  12. R. Ginosar and R. Kol, “Adaptive Synchronization,” Asynchronous Interfaces Workshop (AINT’2000), pp. 93-101, July 2000.

  13. Stevens, S. Rotem, R. Ginosar, P. Beerel, C.J. Myers, K.Y. Yun, R. Kol, C. Dike and M. Roncken, “An Asynchronous Instruction Length Decoder,” IEEE Journal of Solid State Circuits, 36(2), pp. 217-228, Feb. 2001 (an earlier version appeared in ASYNC 1999).

  14. K. S. Stevens, R. Ginosar, S. Rotem, “Relative Timing,”  IEEE Transactions on VLSI, 11(1), pp. 129-140, Feb. 2003.

  15. Y. Elboim, R. Ginosar and A. Kolodny, “A Clock Tuning Circuit for System on Chip,”  IEEE Transactions on VLSI, 11(4), pp. 616 –626, 2003.

  16. Y. Semiat and R.Ginosar, "Timing Measurements of Synchronization Circuits," ASYNC 2003.

  17. A. Morgenshtein, M. Moreinis and R. Ginosar, "Asynchronous Gate-Diffusion-Input (GDI) Circuits," IEEE Transactions on VLSI, 12(8): 847–856, Aug. 2004.

  18. R. Ginosar, "Fourteen Ways to Fool Your Synchronizer," ASYNC 2003.

  19. A. Branover, R. Kol and R. Ginosar, "Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones," DATE 2004.

  20. R. Dobkin, R. Ginosar and C. Sotiriou, "Data Synchronization Issues in GALS SoCs," ASYNC 2004.

  21. U. Frank and R. Ginosar, “A Predictive Synchronizer for Periodic Clock Domains,” PATMOS 2004.

  22. I. Obridko and R. Ginosar, “Low Energy Asynchronous Adders,” ICECS 2004.

  23. I. Obridko and R. Ginosar, “Low Energy Asynchronous Architectures,” ISCAS 2005.

  24. I. Obridko and R. Ginosar, “Low Energy Asynchronous Architectures,” IEEE Trans. on VLSI, 14(9):1043-1047, Sep. 2006.

  25. T. Kapschitz and R.Ginosar, “Formal Verification of Synchronizers,” CCIT Tech. Rep. 536, EE Dept., Technion, 2005.

  26. U. Frank, T. Kapschitz and R. Ginosar, “A Predictive Synchronizer for Periodic Clock Domains,” J. Formal Methods in System Design (special issue on Formal Methods for Globally Asynchronous Locally Synchronous Design), 28(2):171-186, 2006 (SpringerLink).

  27. R. Ginosar, “MTBF of a MultiSynchronizer System on Chip,” 2005.

  28. T. Kapschitz and R.Ginosar, “Formal Verification of Synchronizers,” 13th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME), Germany, Oct. 2005.

  29. T. Liran and R. Ginosar, "All-Digital DLL Architecture and Applications," Technical Report, Sep. 2005.

  30. R. Dobkin, R. Ginosar and C. Sotiriou, "High Rate Data Synchronization in GALS SoCs," IEEE Trans. on VLSI, 14(10):1063-1074, Oct. 2006.

  31. M. Kayam, R. Ginosar and C.E. Dike, "Symmetric Boost Synchronizer for Robust Low Voltage, Low Temperature Operation," Technical Report, Jan. 2007.

  32. R. Dobkin and R. Ginosar , "Zero latency synchronizers using four and two phase protocols," Technical Report, Oct. 2007.

  33. R. Dobkin, T. Kapshitz, S. Flur and R.Ginosar, "Assertion Based Verification of Multiple-Clock GALS Systems," Technical Report, Oct. 2007.

  34. R. Dobkin and R.Ginosar, "Fast Universal Synchronizers," Technical Report, Mar. 2008.

  35. R. Dobkin, T. Kapshitz, S. Flur and R.Ginosar, "Assertion Based Verification of Multiple-Clock GALS Systems," VLSI-SoC, Oct. 2008.

  36. R. Dobkin and R.Ginosar, "Fast Universal Synchronizers," PATMOS, Sep. 2008.

  37. R. Dobkin and R.Ginosar, "Two phase synchronization with sub-cycle latency," INTEGRATION, the VLSI journal, 42(3):367-375, 2009, http://dx.doi.org/10.1016/j.vlsi.2008.11.006

  38. I. Vaisband, R. Ginosar, A. Kolodny, E.G. Friedman, "Power efficient tree-based crosslinks for skew reduction," ACM Great Lakes Symposium on VLSI, May 2009.

  39.  

  40. S. Beer, R. Ginosar, M. Priel, R. Dobkin and A. Kolodny, "The Devolution of Synchronizers," ASYNC 2010.

  41. D. Verbitsky, R. Dobkin and R.Ginosar, "A Four-Stage Mesochronous Synchronizer with Back-Pressure and Buffering for Short and Long Range Communications," Tech. Rep., 2011.

  42. I. Vaisband, E.G. Friedman, R. Ginosar and A. Kolodny, “Low Power Clock Network Design,” J. Low Power Electron. Appl. 2011, 1(1), 219-246; doi:10.3390/jlpea1010219

  43. S. Beer, R. Ginosar, M. Priel, R. Dobkin and A. Kolodny, “An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm,” IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2011.

  44. R. Ginosar, "Metastability and Synchronizers: A Tutorial," IEEE Design & Test, Sept/Oct. 2011.

  45. I. Vaisband, E.G. Friedman, R. Ginosar, A. Kolodny, "Energy metrics for power efficient crosslink and mesh topologies," ISCAS, pp. 1656-1659, 2012.

  46. A. Abdelhadi, R. Ginosar, A. Kolodny, E.G. Friedman, "Timing-driven variation- aware nonuniform clock mesh synthesis," ACM/IEEE Great Lakes Symposium on VLSI, pp. 15–20, 2010.

  47. A. Abdelhadi, R. Ginosar, A. Kolodny and E.G. Friedman, "Timing-driven variation-aware synthesis of hybrid mesh/tree clock distributuion networks," Integration, the VLSI Journal, 2013.

  48.  

  49. S. Beer and R. Ginosar, "An Extended Metastability Simulation Method for Synchronizer Characterization," PATMOS, LNCS 7606, pp. 42-51, 2012.

  50. S. Beer and R. Ginosar, "A new 65nm LP metastability measurment test circuit," IEEE Israel, 2012.

  51. S. Beer and R. Ginosar, "An extended metastability simulation method; Extended nose short simulation (ENSS)," IEEE Israel, 2012.

  52. S. Beer, R. Ginosar, J. Cox, T. Chaney and D.M. Zar, “Metastability challenges for 65nm and beyond: Simulation and measurements,” Design Automation and Test in Europe (DATE), Grenoble, France, March 2013.

  53. S. Beer, R. Ginosar, R. Dobkin and Y. Weizman, "MTBF Estimation in Coherent Clock Domains," Nineteenth IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), Santa Monica, USA, May 2013.

  54. D. Verbitsky, R. Dobkin, S. Beer and R. Ginosar, “StarSync: An Extendable Standard-cell Mesochronous Synchronizer,” accepted for publication, Integration—the VLSI Journal, 2013.

  55. S. Beer and R. Ginosar, “Supply Voltage and Temperature Variations in Synchronization Circuits,” 2013.

(Asynchronous) Network on Chip:

  1. E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny, "QNoC: QoS architecture and design process for network on chip," Special issue on Networks on Chip,  The Journal of Systems Architecture, 50(2-3):105-128, February 2004.

  2. E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny, "Cost considerations in  network on chip," Integration, the VLSI Journal, Vol. 38, No. 1, pp. 19-42, Oct. 2004.

  3. A. Morgenshtein, E. Bolotin, I. Cidon, A. Kolodny, R. Ginosar, “Micro-Modem – Reliability Solution for NoC Communications,” ICECS 2004.

  4. E. Bolotin, A. Morgenshtein, I. Cidon, R. Ginosar and A. Kolodny, “Automatic Hardware-Efficient SoC Integration by QoS Network on Chip,” ICECS 2004.

  5. A. Morgenshtein, I. Cidon, A.Kolodny and R. Ginosar , “Comparative Analysis of Serial vs Parallel Links in Networks on Chip,” SoC 2004.

  6. R. Dobkin, V. Vishnyakov, E. Friedman and R.Ginosar, "An Asynchronous Router for Multiple Service Levels Networks on Chip," ASYNC 2005.

  7. R. Dobkin, I.Cidon, R.Ginosar, A.Kolodny and A.Morgenshtein, "Fast Asynchronous Bit-Serial Interconnects for Network-on-Chip," 2004.

  8. A. Morgenshtein, I.Cidon, A. Kolodny and R. Ginosar, "Low-Leakage Repeaters for NoC Interconnects," ISCAS 2005.

  9. Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, "Efficient Link Capacity and QoS Design for Wormhole Network-on-Chip," DATE, pp. 9-14, March 2006.

  10. E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny, "Efficient Routing in Irregular Topology NoCs," CCIT Report #554, Elec. Eng. Dept, Technion, Sep. 2005.

  11. R. Dobkin, R.Ginosar and A.Kolodny, "Fast Asynchronous Shift Register for Bit-Serial Communication," ASYNC 2006.

  12. E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, “Routing Table Minimization for Irregular Mesh NoCs,” Design Automation and Test in Europe (DATE), Nice, France, March 2007.

  13. R. Dobkin, Y. Perelman, T. Liran, R. Ginosar, and A. Kolodny, “High rate wave-pipelined asynchronous on-chip bit-serial data link,” Thirteenth IEEE International Symposium on Asynchronous Circuits and Systems, Berkeley, USA, March 2007.

  14. R. Dobkin, R. Ginosar and I. Cidon, “QNoC Asynchronous Router with Dynamic Virtual Channel Allocation,” First ACM/IEEE Int. Symp on Networks on Chip (NOCS), May 2007.

  15. A. Morgenshtein, E.G. Friedman, R. Ginosar, A. Kolodny, “Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths with RC Interconnect,” in press, IEEE Trans. on VLSI, 2009.

  16. E. Bolotin, Z. Guz, I. Cidon, R. Ginosar and A. Kolodny, “The Power of Priority: NoC Based Distributed Cache Coherency,” First ACM/IEEE Int. Symp on Networks on Chip (NOCS), May 2007.

  17. I. Walter, I. Cidon, R. Ginosar and A. Kolodny, “Access Regulation To Hot-Modules In Wormhole NoCs,” First ACM/IEEE Int. Symp on Networks on Chip (NOCS), May 2007.

  18. Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar, and Avinoam Kolodny, “Network Delays and Link Capacities in Application-Specific Wormhole NoCs,” The Journal of VLSI Design, special issue on Networks on Chip, 2007(90941), 2007 (http://dx.doi.org/10.1155/2007/90941)

  19. R. Dobkin, A. Morgenshtein, A. Kolodny, R. Ginosar, "Parallel vs. Serial On-Chip Communication," IEEE/ACM Workshop on System Level Interconnect Prediction (SLIP), Newcastle upon Tyne, UK, Apr. 2008.

  20. R. Dobkin, R. Ginosar, A. Kolodny, “QNoC Asynchronous Router," Integration, the VLSI Journal, 42(2):103-115, 2009 (http://dx.doi.org/10.1016/j.vlsi.2008.03.001)

  21. A. Morgenshtein, E.G. Friedman, R. Ginosar and A. Kolodny, “Timing Optimization in Logic with Interconnect,” (invited paper), IEEE/ACM Workshop on System Level Interconnect Prediction (SLIP), Newcastle upon Tyne, UK, Apr. 2008.

  22. R. Dobkin, M. Moyal, A. Kolodny and R. Ginosar, "Asynchronous Current Mode Serial Communication," IEEE Trans. On VLSI, 18(7):1107-1117, 2010.

  23. A. Baron, R. Ginosar and I. Keslassy, "The Capacity Allocation Paradox," IEEE Infocom '09, Rio de Janeiro, Brazil, April 2009.

  24. D. Vainbrand and R. Ginosar, "Network-on-Chip Architectures for Neural Networks," Fourth ACM/IEEE Int. Symp on Networks on Chip (NOCS), May 2010.

  25. D. Vainbrand and R. Ginosar, "Scalable network-on-chip architecture for configurable neural networks" Microprocessors and Microsystems, 35(2):152-166, 2011.

  26. A. Berman, R. Ginosar, I. Keidar, "Order is Power: Selective Packet Interleaving for Energy Efficient Networks-on-Chip," 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC'10), September 2010.

Other VLSI Architectures:

  1. Reuven Dobkin, Michael Peleg and Ran Ginosar, "Parallel VLSI Architecture for MAP Turbo Decoder," 13th IEEE Int. Symp. on Personal, Indoor and Mobile Radio Communications (PIMRC 2002), Lisboa, Portugal, Sep. 2002.

  2. Reuven Dobkin, Michael Peleg and Ran Ginosar, "Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders," IEEE Trans. Very Large Scale Integration (VLSI) Systems, 13(4):427-438,  April 2005.

  3. R. Rom, J. Erel, M. Glikson, K. Rosenblum, R.  Ginosar and D. Hayes, “Adaptive Cardiac Resynchronization Therapy Device: A Simulation Report,” Pacing and Clinical Electrophysiology (PACE), 28(11):1168-1173, 2005.

  4. R. Rom, J. Erel, M. Glikson, R. Lieberman K. Rosenblum, O. Binah, R. Ginosar and D. Hayes, "Adaptive Cardiac Resynchronization Therapy Device Based on Spiking Neurons Architecture and Reinforcement Learning Scheme," IEEE Trans. Neural Networks, 18(2):542-550, 2007.

  5. A. Elyada, R.Ginosar and U.Weiser, "Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors," Technical Report, 2007, and journal version, IEEE Trans. VLSI, 16(9):1243-1248, 2008.

  6. E. Rotem, R. Ginosar, A. Mendelson and U. Weiser, "Multiple Clock and Voltage Domains for Chip Multi Processors," IEEE 42nd International Symposium on Microarchitecture (MICRO), New York, 2009.

  7. F. Sturesson, J. Gaisler, R. Ginosar and T. Liran, “Radiation Characterization of a Dual Core LEON3‑FT Processor,” Conf. on Radiation Effects on Components and Systems (RADECS), Sevilla, Spain, Sep 19-23, 2011.

  8. R. Ginosar, “A Survey of Processors for Space.” Data Systems in Aerospace (DASIA), Dubrovnik, May 2012.

  9. E. Nave and R. Ginosar, "TCP Window Based DVFS for Low Power Network Controller SoC," PATMOS, LNCS 7606, pp. 83-92, 2012.

  10. E. Rotem, R. Ginosar, A. Mendelson and U. Weiser, "Energy Aware Race to Halt: A Down to EARtH Approach to Platform Energy Management," Computer Architecture Letters, 2012.

  11. E. Nave and R. Ginosar, “PBD: Packet Buffer DVFS,” ACM Great Lakes Symposium on VLSI (GLSVLSI), Paris, France, May 2013.

  12. R. Ginosar et al., “Rad-Hard 2.5 Gbps SpaceFibre Interface Device,” Data Systems in Aerospace (DASIA), Porto, May 2013.

  13. E. Rotem, R. Ginosar, U. Weiser and A. Mendelson, "Power and Thermal Constraints of Modern System-on-a-Chip Computer,"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), Berlin, Germany, Sept. 2013.

  14. E. Rotem, R. Ginosar, U. Weiser and A. Mendelson, “H-EARtH: Heterogeneous Platform Energy Management,” 2013.

Patents:

  1. R. Ginosar, Y.Y. Zeevi and O. Hilsenrath, "Intelligent Scan Image Sensor," USA Patent 4,942,473, 1990.

  2. R. Ginosar, Y.Y. Zeevi and O. Hilsenrath, "Intelligent Scan Processor," Israel Patent 87,310, 1988.

  3. R. Ginosar, Y.Y. Zeevi and O. Hilsenrath, "Dynamic Image Representation System," USA Patent 5,420,637, 1995.

  4. R. Ginosar, Y.Y. Zeevi and O. Hilsenrath, "Wide Dynamic Range Camera," USA Patent 5,144,442, 1992.

  5. R. Ginosar, Y.Y. Zeevi and O. Hilsenrath, "Wide Dynamic Range Sensor," Israel Patents 87,307/91,095, 1988; European EP431010A1, 1991.

  6. R. Ginosar, Y.Y. Zeevi, D. Kligler, N. Sorek, T. Genossar and O. Zinaty, "Color Wide Dynamic Range Camera," USA Patent 5,247,366, 1993.

  7. N. Bayer and R. Ginosar, "High flow-rate synchronizer/scheduler apparatus and method for multiprocessors," USA Patent 5,202,987, 1993.

  8. R. Ginosar, Y.Y. Zeevi and S. Wolf, "Apparatus & Method for Enhancing Color Images," USA Patent 5,467,123, 1995.

  9. R. Ginosar, Y.Y. Zeevi, D. Kligler, N. Sorek, T. Genossar and O. Zinaty, "Wide Dynamic Range Mosaic CCD Color Camera," US application, March 1993.

  10. R. Ginosar and N. Weinberg, "VLSI Architecture Based on Neural Network," US patent 5,812,993, 1998.

  11. R. Ginosar and H. Finkelstein, "A Detector of Particle Beams," US application, 1997.

  12. R.Ginosar, R.Kol, K.S. Stevens, P.A. Beerel, K.Y. Yun, C.J. Myers, and S.Rotem, “Efficient Self-Timed Marking of Lengthy Variable Length Instructions,” US Patent 5,941,982, 1999.

  13. R.Ginosar, R.Kol, K.S. Stevens, P.A. Beerel, K.Y. Yun, C.J. Myers, and S.Rotem, “Branch Instruction Handling in a Self-Timed Marking System,” US Patent 5,931,944, 1999.

  14. R.Ginosar, R.Kol, K.S. Stevens, P.A. Beerel, K.Y. Yun, C.J. Myers, and S.Rotem, “Aparatus and Method for Self-Timed Marking of Variable Length Instructions Having Length-Affecting Prefix Bytes,” US Patent 5,948,096, 1999.

  15. R.Ginosar, R.Kol, K.S. Stevens, P.A. Beerel, K.Y. Yun, C.J. Myers, and S.Rotem, “Aparatus and Method for Parallel Processing and Self-Timed Serial Marking of Variable Length Instructions,” US Patent 5,978,899, 1999.

  16. K. Stevens, S. Rotem and R. Ginosar, “Circuit Synthesis and Verification Using Relative Timing,” US Patent 6,314,553, 2001.

  17. R. Ginosar, "Dual-Function Computing System Having Instant-On Mode of Operation," US Patent 6,931,474, 2005.

  18. R. Ginosar, "Computing Device Capable of Instant-On and Non-Instant-On Modes of Operation," US Patent 7,096,309, 2006.

  19. R. Ginosar, “Dual Form Low Power, Instant On And High Performance, Non-Instant On Computing Device,” US Patent 7,098,899, 2006.

  20. E. Zehavi, R. Ginosar, R. Nevo and B. Monello, “Multiple Wireless Communication Protocol Methods And Apparatuses,” US Patent 6,600,726, 2003.

  21. Y. Elboim, A. Kolodny and R. Ginosar, “Clock Tuning Circuit in Chip Design,” US Patent Application 2002/0073389 A1, 2000.

  22. R. Nevo, E. Zehavi, X. Zhao and R. Ginosar, “Multiple Wireless Communication Protocol Methods And Apparatuses Including Proactive Reduction Of Interference,” US Patent 6,891,857, 2005.

  23. R. Ginosar and Y. Perelman,  “An Integrated System and Method for Multichannel Neuronal Recording with Spike/Lfp Separation, Integrated A/D Conversion and Threshold Detection,” US Patent , 8,090,674, Jan. 3, 2012.

  24. R. Ginosar, A. Zviaguintsev and Y. Perelman, “Low Power Hardware Algorithms and Architectures for Spike Sorting and Detection,” US Patent Application 2009/0124919 A1, July 2004.

  25. R. Ginosar and Y. Perelman, “A Low Power Inverted Ladder Digital to Analog Converter,”  US Patent 7,554,475 B2, 2009.

  26. R. Dobkin and R. Ginosar, “System and Method for Synchronizing Multi-Clock Domains,” U.S. Patent Application 2010/0322365A1, June 18, 2009.

  27. A. Morgenshtein, R. Ginosar, A. Kolodny and E.G. Friedman, “Logic Circuit Delay Optimization,” U.S. Patent 8,225,265, Jul. 17, 2012.