Publications - Ran Ginosar

Copyright notice: This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.    For papers published by the IEEE: Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution or servers or lists or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

Last Update: 01 August, 2017

2017

·         Leonid Yavits, Ran Ginosar, Sparse Matrix Multiplication on CAM Based Accelerator, 2017, https://arxiv.org/abs/1705.09937 .

·         L Yavits, A Morad, U Weiser, R Ginosar, MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures, 2017, https://arxiv.org/abs/1705.06923 .

·         Leonid Azriel, Ran Ginosar, Avi Mendelson, Revealing On-chip Proprietary Security Functions with Scan Side Channel Based Reverse Engineering, Proceedings of the Great Lakes Symposium on VLSI, 2017

·         Azriel, Leonid, Ran Ginosar, Shay Gueron, and Avi Mendelson. Using Scan Side Channel to Detect IP Theft. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2017).

·         L Yavits, U Weiser, R Ginosar, Resistive Address Decoder, IEEE Computer Architecture Letter, 2017

·         R Kaplan, L Yavits, R Ginosar, U Weiser, A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment, Memristor Technology, Design, Automation and Computing workshop, HiPEAC 2017, https://arxiv.org/abs/1701.04723 .

·         R Kaplan, L Yavits, R Ginosar, U Weiser, A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment, IEEE Micro, July-August 2017.

·         L. Yavits, R. Ginosar, Accelerator for Sparse Machine Learning, IEEE Computer Architecture Letters, 2017.

·         L. Yavits, R. Kaplan, and R. Ginosar, In-Data vs. Near Data processing: The case for Resistive CAM Processing in Storage, 2017.

·         R. Kaplan, L. Yavits, and R. Ginosar, From Processing-in-Memory to Processing-In-Storage, 2017.

·         R. Kaplan, L. Yavits, R. Ginosar, In-Storage Implementation of K-Means in Resistive CAM, International Conference on Memristive Materials, Devices & Systems, 2017.

2016

·         Rotem, Efraim, Uri C. Weiser, Avi Mendelson, Ran Ginosar, Eliezer Weissmann and Yoni Aizik. H-EARtH: Heterogeneous Multicore Platform Energy Management. Computer 49, no. 10 (2016): 47-55.

·         Kaplan, Roman, Leonid Yavits, Amir Morad, and Ran Ginosar. Deduplication in resistive content addressable memory based solid state drive. In 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 100-106. IEEE, 2016.

·         Ginosar, Ran, Yevgeny Perelman, and Alex Zviagintsev. Low power hardware algorithms and architectures for spike sorting and detection. U.S. Patent 9,449,225, issued September 20, 2016. http://www.google.com/patents/US9449225.

·         Azriel, Leonid, Ran Ginosar, Shay Gueron, and Avi Mendelson. Using Scan Side Channel for Detecting IP Theft. In Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, p. 1. ACM, 2016.

·         Azriel, Leonid, Abraham Mendelson, and Ran Ginosar. Exploiting the scan test interface for reverse engineering of a VLSI device. U.S. Patent Application 15/145,988, filed May 4, 2016. http://www.google.com/patents/US20160328509.

·         Aviely, Peleg, Olga Radovsky, and Ran Ginosar. DVB-S2 software defined radio modem on the RC64 manycore DSP. In Aerospace Conference, 2016 IEEE, pp. 1-10. IEEE, 2016.

·         Ginosar, Ran, Peleg Aviely, Tsvika Israeli, and Henri Meirov. RC64: High performance rad-hard manycore. In Aerospace Conference, 2016 IEEE, pp. 1-9. IEEE, 2016.

·         R. Kaplan, L. Yavits, and R. Ginosar, An In-Storage Implementation of Smith-Waterman in Resistive CAM, In-Memory and In-Storage Computing with Emerging Technologies workshop, PACT 2016.

·         Yavits, Leonid, Amir Morad, and Ran Ginosar. Effect of Data Sharing on Private Cache Design in Chip Multiprocessors. https://arxiv.org/abs/1602.01329 .

·         Yavits, Leonid, Amir Morad, Ran Ginosar, and U. Weiser. Convex Optimization of Real Time SoC. https://arxiv.org/abs/1601.07815 .

·         Morad, Amir, Leonid Yavits, Shahar Kvatinsky, and Ran Ginosar. Hybrid processor. U.S. Patent Application 14/989,880, filed January 7, 2016. https://www.google.com/patents/US20160224465.

·         Morad, Amir, Leonid Yavits, Shahar Kvatinsky, and Ran Ginosar. Resistive GP-SIMD processing-in-memory. ACM Transactions on Architecture and Code Optimization (TACO) 12, no. 4 (2016): 57.

2015

·         L. Yavits, A. Morad, R. Ginosar, Computer Architecture with Associative Processor Replacing Last Level Cache and SIMD Accelerator, IEEE Transactions on Computers, 64(2):368-381, 2015.

·         Beer, S. and Ginosar, R., Eleven ways to boost your synchronizer, IEEE Transactions on VLSI, 23(6):1040-1049, 2015.

·         Yavits, L., Morad, A. and Ginosar, R., Sparse Matrix Multiplication on an Associative Processor, IEEE Transactions on Parallel and Distributed Systems, 26(11):3175-3183, 2015.

·         S. Beer and R. Ginosar, A Model for Supply Voltage and Temperature Variation Effects on Synchronizer Performance, IEEE Transactions on VLSI, 23(11):2461-2472, 2015.

·         S. Beer, J. Cox, R. Ginosar, T. Chaney and D.M. Zar, Variability in Multistage Synchronizers, IEEE Transactions on VLSI, 23(12):2957-2969, 2015.

·         Yavits, Leonid, Amir Morad, and Ran Ginosar, The Effect of Temperature on Amdahl Law in 3D Multicore Era, accepted for publication, IEEE Transactions on Computers, 2015.

·         Morad, L. Yavits, S. Kvatinsky and R. Ginosar, Resistive GP-SIMD Processing-in-Memory, accepted for publication, ACM Transactions on Architecture and Code Optimization (TACO), 2015.

·         R. Ginosar, Accelerators for Machine Learning of Big Data, Computer Architecture For Machine Learning (CAMEL) Workshop, Portland, OR., June 2015 (invited paper).

·         I. Avron and R. Ginosar, Hardware Scheduler Performance on the Plural Many-Core Architecture, 3rd ACM International Workshop on Manycore Embedded Systems (MES), Portland, OR., June 2015.

·         E. Rotem, R. Ginosar, U. Weiser and A. Mendelson, Power and Thermal Constraints of Modern System-on-a-Chip Computer, Microelectronics Journal, 46(12):1225-1229, 2015.

2014

·         E. Rotem, U. Weiser, A. Mendelson, A. Yassin and R. Ginosar, Energy management of highly dynamic server workloads in a heterogeneous data center, PATMOS, 2014.

·         A. Morad, L. Yavits and R. Ginosar, Efficient Dense and Sparse Matrix Multiplication on GP-SIMD, PATMOS, 2014.

·         A. Morad, L. Yavits and R. Ginosar, Convex Optimization of Resource Allocation in Asymmetric and Heterogeneous SoC, PATMOS, 2014.

·         A. Morad, L. Yavits and R. Ginosar, GP-SIMD Processing-in-Memory, ACM Transactions on Architecture and Code Optimization (TACO), 11(4):53, 2014.

·         A. Morad, L. Yavits and R. Ginosar, Convex Optimization of Resource Allocation in Asymmetric and Heterogeneous MultiCores, 2014.

·         J. Haj-Yihia, Y. Ben-Asher, E. Rotem, A. Yasin and R. Ginosar, Compiler-Directed Power Management for Superscalars, ACM Transactions on Architecture and Code Optimization(TACO), 11(4):48, 2014.

·         L. Yavits, S. Kvatinsky, A. Morad, R. Ginosar, Resistive Associative Processor, IEEE Computer Architecture Letters, 2014.

·         L. Yavits, A. Morad, R. Ginosar, The Effect of Communication and Synchronization on Amdahl's Law in Multicore Systems, Journal of Parallel Computing, 40.1:1-16, 2014.

·         D. Verbitsky, R. Dobkin, S. Beer and R. Ginosar, StarSync: An Extendable Standard-cell Mesochronous Synchronizer, Integration—the VLSI Journal, 47.2:250-260, 2014.

·         L. Yavits, A. Morad, R. Ginosar, Cache Hierarchy Optimization, Computer Architecture Letters, 13(2):69-72, 2014.

·         E. Rotem, R. Ginosar, A. Mendelson and U. Weiser, Energy Aware Race to Halt: A Down to EARtH Approach to Platform Energy Management, Computer Architecture Letters, 13(1):25-28, 2014.

·         Morad, T. Morad, L. Yavits, R. Ginosar and U. Weiser, Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC, Computer Architecture Letters, 13(1):37-40, 2014.

·         Beer, S., Cannizzaro, M., Cortadella, J., Ginosar, R., & Lavagno, L., Metastability in better-than-worst-case designs, 2014 20th IEEE International Symposium on  Asynchronous Circuits and Systems (ASYNC), pp. 101-102, May 2014.

·         A. Morad, L. Yavits and R. Ginosar, Efficient Dense and Sparse Matrix Multiplication on GP-SIMD, Power and Timing Modeling, Optimization and Simulation (PATMOS), Palma de Majorca, 2014.

·         A. Morad, L. Yavits and R. Ginosar, Convex Optimization of Resource Allocation in Asymmetric and Heterogeneous SoC, Power and Timing Modeling, Optimization and Simulation (PATMOS), Palma de Majorca, 2014.

·         E. Rotem, U. Weiser, A. Mendelson, A. Yassin and R. Ginosar, Energy management of highly dynamic server workloads in an heterogeneous data center, Power and Timing Modeling, Optimization and Simulation (PATMOS), Palma de Majorca, 2014.

2013

·         L. Yavits, A. Morad, R. Ginosar and E.G. Friedman, Associative Processor Thermally Enables 3-D Integration of Processing and Memory, 2013.

·         Morad, T. Morad, L. Yavits and R. Ginosar, Optimization of Asymmetric and Heterogeneous MultiCore, 2013.

·         L. Yavits, A. Morad and R. Ginosar, 3D Cache Hierarchy Optimization, 3DIC conference, San Francisco, USA, Oct. 2013.

·         R. Ginosar, Mathematical modeling of many-cores, Shonan workshop on Many-Cores and On-Chip Interconnects, Shonan Village Center, Japan, Sept. 2013.

·         R. Ginosar, The Plural Architecture: Shared Memory Many-cores with Hardware Scheduling, IEEE 7th Int. Symp. On Embedded Multicore/Manycore SoCs (MCSoC), Tokyo, Japan, Sept. 2013 (invited keynote speech).

·         S. Beer and R. Ginosar, Supply Voltage and Temperature Variations in Synchronization Circuits, 2013.

·         S. Beer, R. Ginosar, R. Dobkin and Y. Weizman, MTBF Estimation in Coherent Clock Domains, Nineteenth IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), Santa Monica, USA, May 2013.

·         S. Beer, R. Ginosar, J. Cox, T. Chaney and D.M. Zar, Metastability challenges for 65nm and beyond: Simulation and measurements, Design Automation and Test in Europe (DATE), Grenoble, France, March 2013.

·         Abdelhadi, R. Ginosar, A. Kolodny and E.G. Friedman, Timing-driven variation-aware synthesis of hybrid mesh/tree clock distributuion networks, Integration - the VLSI Journal, 46.4:382-391, 2013.

·         E. Rotem, R. Ginosar, U. Weiser and A. Mendelson, H-EARtH: Heterogeneous Platform Energy Management, 2013.

·         E. Rotem, R. Ginosar, U. Weiser and A. Mendelson, Power and Thermal Constraints of Modern System-on-a-Chip Computer, 19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), Berlin, Germany, Sept. 2013.

·         R. Ginosar et al., Rad-Hard 2.5 Gbps SpaceFibre Interface Device, Data Systems in Aerospace (DASIA), Porto, May 2013.

·         E. Nave and R. Ginosar, PBD: Packet Buffer DVFS, ACM Great Lakes Symposium on VLSI (GLSVLSI), Paris, France, May 2013.

2012

·         Avron and R. Ginosar, Performance of a Hardware Scheduler for Many-core Architecture, HPCC-ICESS 2012, pp. 151-160.

·         S. Beer and R. Ginosar, An extended metastability simulation method; Extended nose short simulation (ENSS), IEEE Israel, 2012.

·         S. Beer and R. Ginosar, A new 65nm LP metastability measurment test circuit, IEEE Israel, 2012.

·         S. Beer and R. Ginosar, An Extended Metastability Simulation Method for Synchronizer Characterization, PATMOS, LNCS 7606, pp. 42-51, 2012.

·         Vaisband, E.G. Friedman, R. Ginosar, A. Kolodny, Energy metrics for power efficient crosslink and mesh topologies, ISCAS, pp. 1656-1659, 2012.

·         E. Nave and R. Ginosar, TCP Window Based DVFS for Low Power Network Controller SoC, PATMOS, LNCS 7606, pp. 83-92, 2012.

·         R. Ginosar, A Survey of Processors for Space. Data Systems in Aerospace (DASIA), Dubrovnik, May 2012.

·         A. Morgenshtein, R. Ginosar, A. Kolodny and E.G. Friedman, Logic Circuit Delay Optimization, U.S. Patent 8,225,265, Jul. 17, 2012.

·         R. Ginosar and Y. Perelman,  An Integrated System and Method for Multichannel Neuronal Recording with Spike/Lfp Separation, Integrated A/D Conversion and Threshold Detection, US Patent , 8,090,674, Jan. 3, 2012.

2011

·         D. Khoretz, E. Friedman and R. Ginosar, HyperCoreX: Non-Equidistant Memory Network in a Many-core Architecture, Technical Report, 2011.

·         R. Ginosar, Metastability and Synchronizers: A Tutorial, IEEE Design & Test, Sept/Oct. 2011.

·         S. Beer, R. Ginosar, M. Priel, R. Dobkin and A. Kolodny, An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm, IEEE Int. Symp. on Circuits and Systems (ISCAS), May 2011.

·         Vaisband, E.G. Friedman, R. Ginosar and A. Kolodny, Low Power Clock Network Design, J. Low Power Electron. Appl. 2011, 1(1), 219-246; doi:10.3390/jlpea1010219

·         D. Verbitsky, R. Dobkin and R.Ginosar, A Four-Stage Mesochronous Synchronizer with Back-Pressure and Buffering for Short and Long Range Communications, Tech. Rep., 2011.

·         D. Vainbrand and R. Ginosar, Scalable network-on-chip architecture for configurable neural networks Microprocessors and Microsystems, 35(2):152-166, 2011.

·         F. Sturesson, J. Gaisler, R. Ginosar and T. Liran, Radiation Characterization of a Dual Core LEON3‑FT Processor, Conf. on Radiation Effects on Components and Systems (RADECS), Sevilla, Spain, Sep 19-23, 2011.

2010

·         A. Abdelhadi, R. Ginosar, A. Kolodny, E.G. Friedman, Timing-driven variation- aware nonuniform clock mesh synthesis, ACM/IEEE Great Lakes Symposium on VLSI, pp. 15–20, 2010.

·         S. Beer, R. Ginosar, M. Priel, R. Dobkin and A. Kolodny, The Devolution of Synchronizers, ASYNC 2010.

·         A. Berman, R. Ginosar, I. Keidar, Order is Power: Selective Packet Interleaving for Energy Efficient Networks-on-Chip, 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC'10), September 2010.

·         D. Vainbrand and R. Ginosar, Network-on-Chip Architectures for Neural Networks, Fourth ACM/IEEE Int. Symp on Networks on Chip (NOCS), May 2010.

·         R. Dobkin, M. Moyal, A. Kolodny and R. Ginosar, Asynchronous Current Mode Serial Communication, IEEE Trans. On VLSI, 18(7):1107-1117, 2010.

2009

·         R. Ginosar, Many-cores: Supercomputer-on-chip, presentation at the Israel CMP Day III, 3 Feb 2009.

·         Vaisband, R. Ginosar, A. Kolodny, E.G. Friedman, Power efficient tree-based crosslinks for skew reduction, ACM Great Lakes Symposium on VLSI, May 2009.

·         R. Dobkin and R.Ginosar, Two phase synchronization with sub-cycle latency, INTEGRATION, the VLSI journal, 42(3):367-375, 2009, http://dx.doi.org/10.1016/j.vlsi.2008.11.006

·         A. Baron, R. Ginosar and I. Keslassy, The Capacity Allocation Paradox, IEEE Infocom '09, Rio de Janeiro, Brazil, April 2009.

·         R. Dobkin, R. Ginosar, A. Kolodny, QNoC Asynchronous Router, Integration, the VLSI Journal, 42(2):103-115, 2009 (http://dx.doi.org/10.1016/j.vlsi.2008.03.001)

·         Morgenshtein, E.G. Friedman, R. Ginosar, A. Kolodny, Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths with RC Interconnect, in press, IEEE Trans. on VLSI, 2009.

·         E. Rotem, R. Ginosar, A. Mendelson and U. Weiser, Multiple Clock and Voltage Domains for Chip Multi Processors, IEEE 42nd International Symposium on Microarchitecture (MICRO), New York, 2009.

·         R. Dobkin and R. Ginosar, System and Method for Synchronizing Multi-Clock Domains, U.S. Patent Application 2010/0322365A1, June 18, 2009.

·         R. Ginosar and Y. Perelman, A Low Power Inverted Ladder Digital to Analog Converter,  US Patent 7,554,475 B2, 2009.

2008

·         Y. Perelman and R. Ginosar, The NeuroProcessor: An Integrated Interface to Biological Neural Networks, Springer, 2008.

·         R. Dobkin and R.Ginosar, Fast Universal Synchronizers, PATMOS, Sep. 2008.

·         R. Dobkin, T. Kapshitz, S. Flur and R.Ginosar, Assertion Based Verification of Multiple-Clock GALS Systems, VLSI-SoC, Oct. 2008.

·         R. Dobkin and R.Ginosar, Fast Universal Synchronizers, Technical Report, Mar. 2008.

·         Morgenshtein, E.G. Friedman, R. Ginosar and A. Kolodny, Timing Optimization in Logic with Interconnect, (invited paper), IEEE/ACM Workshop on System Level Interconnect Prediction (SLIP), Newcastle upon Tyne, UK, Apr. 2008.

·         R. Dobkin, A. Morgenshtein, A. Kolodny, R. Ginosar, Parallel vs. Serial On-Chip Communication, IEEE/ACM Workshop on System Level Interconnect Prediction (SLIP), Newcastle upon Tyne, UK, Apr. 2008.

·         Elyada, R.Ginosar and U.Weiser, Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors, Technical Report, 2007, and journal version, IEEE Trans. VLSI, 16(9):1243-1248, 2008.

2007

·         R. Dobkin, T. Kapshitz, S. Flur and R.Ginosar, Assertion Based Verification of Multiple-Clock GALS Systems, Technical Report, Oct. 2007.

·         R. Dobkin and R. Ginosar , Zero latency synchronizers using four and two phase protocols, Technical Report, Oct. 2007.

·         M. Kayam, R. Ginosar and C.E. Dike, Symmetric Boost Synchronizer for Robust Low Voltage, Low Temperature Operation, Technical Report, Jan. 2007.

·         Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar, and Avinoam Kolodny, Network Delays and Link Capacities in Application-Specific Wormhole NoCs, The Journal of VLSI Design, special issue on Networks on Chip, 2007(90941), 2007 (http://dx.doi.org/10.1155/2007/90941)

·         Walter, I. Cidon, R. Ginosar and A. Kolodny, Access Regulation To Hot-Modules In Wormhole NoCs, First ACM/IEEE Int. Symp on Networks on Chip (NOCS), May 2007.

·         E. Bolotin, Z. Guz, I. Cidon, R. Ginosar and A. Kolodny, The Power of Priority: NoC Based Distributed Cache Coherency, First ACM/IEEE Int. Symp on Networks on Chip (NOCS), May 2007.

·         R. Dobkin, R. Ginosar and I. Cidon, QNoC Asynchronous Router with Dynamic Virtual Channel Allocation, First ACM/IEEE Int. Symp on Networks on Chip (NOCS), May 2007.

·         R. Dobkin, Y. Perelman, T. Liran, R. Ginosar, and A. Kolodny, High rate wave-pipelined asynchronous on-chip bit-serial data link, Thirteenth IEEE International Symposium on Asynchronous Circuits and Systems, Berkeley, USA, March 2007.

·         E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, Routing Table Minimization for Irregular Mesh NoCs, Design Automation and Test in Europe (DATE), Nice, France, March 2007.

·         R. Rom, J. Erel, M. Glikson, R. Lieberman K. Rosenblum, O. Binah, R. Ginosar and D. Hayes, Adaptive Cardiac Resynchronization Therapy Device Based on Spiking Neurons Architecture and Reinforcement Learning Scheme, IEEE Trans. Neural Networks, 18(2):542-550, 2007.

2006

·         R. Dobkin, R. Ginosar and C. Sotiriou, High Rate Data Synchronization in GALS SoCs, IEEE Trans. on VLSI, 14(10):1063-1074, Oct. 2006.

·         U. Frank, T. Kapschitz and R. Ginosar, A Predictive Synchronizer for Periodic Clock Domains, J. Formal Methods in System Design (special issue on Formal Methods for Globally Asynchronous Locally Synchronous Design), 28(2):171-186, 2006 (SpringerLink).

·         Obridko and R. Ginosar, Low Energy Asynchronous Architectures, IEEE Trans. on VLSI, 14(9):1043-1047, Sep. 2006.

·         R. Dobkin, R.Ginosar and A.Kolodny, Fast Asynchronous Shift Register for Bit-Serial Communication, ASYNC 2006.

·         Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, Efficient Link Capacity and QoS Design for Wormhole Network-on-Chip, DATE, pp. 9-14, March 2006.

·         R. Ginosar, Dual Form Low Power, Instant On And High Performance, Non-Instant On Computing Device, US Patent 7,098,899, 2006.

·         R. Ginosar, Computing Device Capable of Instant-On and Non-Instant-On Modes of Operation, US Patent 7,096,309, 2006.

2005

·         T. Liran and R. Ginosar, All-Digital DLL Architecture and Applications, Technical Report, Sep. 2005.

·         T. Kapschitz and R.Ginosar, Formal Verification of Synchronizers, 13th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME), Germany, Oct. 2005.

·         R. Ginosar, MTBF of a MultiSynchronizer System on Chip, 2005.

·         T. Kapschitz and R.Ginosar, Formal Verification of Synchronizers, CCIT Tech. Rep. 536, EE Dept., Technion, 2005.

·         Obridko and R. Ginosar, Low Energy Asynchronous Architectures, ISCAS 2005.

·         E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny, Efficient Routing in Irregular Topology NoCs, CCIT Report #554, Elec. Eng. Dept, Technion, Sep. 2005.

·         A. Morgenshtein, I.Cidon, A. Kolodny and R. Ginosar, Low-Leakage Repeaters for NoC Interconnects, ISCAS 2005.

·         R. Dobkin, V. Vishnyakov, E. Friedman and R.Ginosar, An Asynchronous Router for Multiple Service Levels Networks on Chip, ASYNC 2005.

·         R. Rom, J. Erel, M. Glikson, K. Rosenblum, R.  Ginosar and D. Hayes, Adaptive Cardiac Resynchronization Therapy Device: A Simulation Report, Pacing and Clinical Electrophysiology (PACE), 28(11):1168-1173, 2005.

·         Reuven Dobkin, Michael Peleg and Ran Ginosar, Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders, IEEE Trans. Very Large Scale Integration (VLSI) Systems, 13(4):427-438,  April 2005.

·         R. Nevo, E. Zehavi, X. Zhao and R. Ginosar, Multiple Wireless Communication Protocol Methods And Apparatuses Including Proactive Reduction Of Interference, US Patent 6,891,857, 2005.

·         R. Ginosar, Dual-Function Computing System Having Instant-On Mode of Operation, US Patent 6,931,474, 2005.

2004

·         Obridko and R. Ginosar, Low Energy Asynchronous Adders, ICECS 2004.

·         U. Frank and R. Ginosar, A Predictive Synchronizer for Periodic Clock Domains, PATMOS 2004.

·         R. Dobkin, R. Ginosar and C. Sotiriou, Data Synchronization Issues in GALS SoCs, ASYNC 2004.

·         A. Branover, R. Kol and R. Ginosar, Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones, DATE 2004.

·         A. Morgenshtein, M. Moreinis and R. Ginosar, Asynchronous Gate-Diffusion-Input (GDI) Circuits, IEEE Transactions on VLSI, 12(8): 847–856, Aug. 2004.

·         R. Dobkin, I.Cidon, R.Ginosar, A.Kolodny and A.Morgenshtein, Fast Asynchronous Bit-Serial Interconnects for Network-on-Chip, 2004.

·         A. Morgenshtein, I. Cidon, A.Kolodny and R. Ginosar , Comparative Analysis of Serial vs Parallel Links in Networks on Chip, SoC 2004.

·         E. Bolotin, A. Morgenshtein, I. Cidon, R. Ginosar and A. Kolodny, Automatic Hardware-Efficient SoC Integration by QoS Network on Chip, ICECS 2004.

·         Morgenshtein, E. Bolotin, I. Cidon, A. Kolodny, R. Ginosar, Micro-Modem – Reliability Solution for NoC Communications, ICECS 2004.

·         E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny, Cost considerations in  network on chip, Integration, the VLSI Journal, Vol. 38, No. 1, pp. 19-42, Oct. 2004.

·         E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny, QNoC: QoS architecture and design process for network on chip, Special issue on Networks on Chip,  The Journal of Systems Architecture, 50(2-3):105-128, February 2004.

·         R. Ginosar, A. Zviaguintsev and Y. Perelman, Low Power Hardware Algorithms and Architectures for Spike Sorting and Detection, US Patent Application 2009/0124919 A1, July 2004.

2003

·         R. Ginosar, Fourteen Ways to Fool Your Synchronizer, ASYNC 2003.

·         Y. Semiat and R.Ginosar, Timing Measurements of Synchronization Circuits, ASYNC 2003.

·         Y. Elboim, R. Ginosar and A. Kolodny, A Clock Tuning Circuit for System on Chip,  IEEE Transactions on VLSI, 11(4), pp. 616 –626, 2003.

·         K. S. Stevens, R. Ginosar, S. Rotem, Relative Timing,  IEEE Transactions on VLSI, 11(1), pp. 129-140, Feb. 2003.

·         E. Zehavi, R. Ginosar, R. Nevo and B. Monello, Multiple Wireless Communication Protocol Methods And Apparatuses, US Patent 6,600,726, 2003.

2002

·         Bayer, N. and R. Ginosar, Tightly Coupled Multiprocessing: The Super Processor Architecture, in Q. Jin, J. Li, N. Zhang, J. Cheng, C. Yu and S. Noguchi (ed.), Enabling Society with Information Technology, Springer, pp. 329-339, 2002.

·         Reuven Dobkin, Michael Peleg and Ran Ginosar, Parallel VLSI Architecture for MAP Turbo Decoder, 13th IEEE Int. Symp. on Personal, Indoor and Mobile Radio Communications (PIMRC 2002), Lisboa, Portugal, Sep. 2002.

2001

·         Perelman, Y. and R. Ginosar, A Low-Light Level Sensor for Medical Diagnostic Applications, IEEE Journal of Solid State Circuits, 36(10), pp. 1553-1558, Oct. 2001.

·         Stevens, S. Rotem, R. Ginosar, P. Beerel, C.J. Myers, K.Y. Yun, R. Kol, C. Dike and M. Roncken, An Asynchronous Instruction Length Decoder, IEEE Journal of Solid State Circuits, 36(2), pp. 217-228, Feb. 2001 (an earlier version appeared in ASYNC 1999).

·         K. Stevens, S. Rotem and R. Ginosar, Circuit Synthesis and Verification Using Relative Timing, US Patent 6,314,553, 2001.

2000

·         R. Ginosar and R. Kol, Adaptive Synchronization, Asynchronous Interfaces Workshop (AINT’2000), pp. 93-101, July 2000.

·         Y. Elboim, A. Kolodny and R. Ginosar, Clock Tuning Circuit in Chip Design, US Patent Application 2002/0073389 A1, 2000.

1999

·         Friedman, A. Arbel and R. Ginosar, The Current Skimming-Based CMOS Readout Architectures for Quantum Well Infrared Photodetectors, 1999 IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, Kanagawa, Japan, June 1999.

·         R.Ginosar, R.Kol, K.S. Stevens, P.A. Beerel, K.Y. Yun, C.J. Myers, and S.Rotem, Aparatus and Method for Parallel Processing and Self-Timed Serial Marking of Variable Length Instructions, US Patent 5,978,899, 1999.

·         R.Ginosar, R.Kol, K.S. Stevens, P.A. Beerel, K.Y. Yun, C.J. Myers, and S.Rotem, Aparatus and Method for Self-Timed Marking of Variable Length Instructions Having Length-Affecting Prefix Bytes, US Patent 5,948,096, 1999.

·         R.Ginosar, R.Kol, K.S. Stevens, P.A. Beerel, K.Y. Yun, C.J. Myers, and S.Rotem, Branch Instruction Handling in a Self-Timed Marking System, US Patent 5,931,944, 1999.

·         R.Ginosar, R.Kol, K.S. Stevens, P.A. Beerel, K.Y. Yun, C.J. Myers, and S.Rotem, Efficient Self-Timed Marking of Lengthy Variable Length Instructions, US Patent 5,941,982, 1999.

1998

·         U. Zangi and R. Ginosar,  A Low Power Video Processor, Int. Symp. on Low Power Electronic Design, Monterey, CA, Aug. 1998.

·         H. Finkelstein and R. Ginosar, Frontside bombarded metal-plated CMOS electron sensor, SPIE 3301: Solid State Sensor Arrays: Development and Applications II, Jan. 1998.

·         S. Wolf, R. Ginosar and Y.Y. Zeevi, Spatio-Chromatic Image Enhancement Based on a Model of Human Visual Information Processing , J. Visual Communication and Image Representation, 9(1), March 1998, pp. 25-37.

·         R. Kol, R. Ginosar and H. Shafi, Avid Execution on the Asynchronous Processor KIN, 3rd Euromicro Conference on Massively Parallel Computing Systems (MPCS’98), Apr. 1998.

·         R. Kol and R. Ginosar, KIN--An Asynchronous Processor, 12th ACM International Conference on Supercomputing (ICS’98), Jul. 1998.

·         R. Kol and R. Ginosar, Adaptive Synchronization, IEEE International Conference on Computer Design (ICCD), Oct. 1998.

·         WC. Chou, P.Beerel, R. Ginosar, R. Kol, C. Myers, S. Rotem, K. Stevens and K. Yun, Average-case optimized technology mapping of one-hot domino circuits, ASYNC 1998

·         R. Ginosar and N. Weinberg, VLSI Architecture Based on Neural Network, US patent 5,812,993, 1998.

1997

·         R. Ginosar and A. Gnusin, Adaptive Sensitivity CMOS Image, IEEE Workshop on CCD and Advanced Image Sensors, Belgium, June 1997.

·         R. Kol and R. Ginosar,  A Doubly-Latched Asynchronous Pipeline, IEEE International Conference on Computer Design (ICCD), Oct. 1997.

·         R. Kol, Self- Timed Asynchronous Architecture of an Advanced General Purpose Microprocessor, PhD Thesis, Sept. 1997.

·         R. Kol, R. Ginosar and G. Samuel, Statechart Methodology for the Design, Validation, and Synthesis of Large Scale Asynchronous Systems,  IEICE Transactions, March 1997.

·         R. Ginosar and H. Finkelstein, A Detector of Particle Beams, US application, 1997.

1996

·         R. Ginosar and S. Chen, Adaptive Sensitivity TDI CCD Image Sensor, EuroOpt / SPIE workshop on Advanced Focal Plane Arrays and Electronic Cameras, Germany, Oct. 1996.

1995

·         M. Sherman and R. Ginosar, Intelligent Scan, Israel IEEE Conf., 1995.

·         Adaptive Sensitity, 1995.

·         S. Chen, R. Ginosar, Adaptive Sensitivity CCD Image Sensor, SPIE 2415: CCD and Solid Sate Optical Sensors V, San Jose, CA, Feb. 1995.

·         David, R. Ginosar, and M. Yoeli, Self-Timed is Self-Checking, Journal on Electronic Testing: Theory and Applications, 6, April 1995, pp. 219-228.

·         R. Ginosar, Y.Y. Zeevi and S. Wolf, Apparatus & Method for Enhancing Color Images, USA Patent 5,467,123, 1995.

·         R. Ginosar, Y.Y. Zeevi and O. Hilsenrath, Dynamic Image Representation System, USA Patent 5,420,637, 1995.

1994

·         L. Yavits, Architecture and design of an associative processor chip for image processing and computer vision, MSc thesis, EE, Technion, 1994.

1993

·         David, I., Ginosar, R. and Yoeli, M., Self-timed Architecture of a Reduced Instruction Set Computer, Manchester Workshop on Asynchronous Logic, March 1993.

·         R. Ginosar, Y.Y. Zeevi, D. Kligler, N. Sorek, T. Genossar and O. Zinaty, Wide Dynamic Range Mosaic CCD Color Camera, US application, March 1993.

·         N. Bayer and R. Ginosar, High flow-rate synchronizer/scheduler apparatus and method for multiprocessors, USA Patent 5,202,987, 1993.

·         R. Ginosar, Y.Y. Zeevi, D. Kligler, N. Sorek, T. Genossar and O. Zinaty, Color Wide Dynamic Range Camera, USA Patent 5,247,366, 1993.

1992

·         David, R. Ginosar, and M. Yoeli, Implementing Sequential Machines as Self-Timed Circuits,'' IEEE Trans. Computers, Jan. 1992.

·         David, R. Ginosar, and M. Yoeli, An Efficient Implementation of Boolean Functions as Self-Timed Circuits,'' IEEE Trans. Computers, Jan. 1992.

·         R. Ginosar, Y.Y. Zeevi and O. Hilsenrath, Wide Dynamic Range Camera, USA Patent 5,144,442, 1992.

1991

·         O. Yadid-Pecht, R. Ginosar, and Y. Shacham-Diamand, A Random Access Photodiode Array for Intelligent Image Capture, IEEE Transactions on Electron Devices, 38(8), pp. 1772-1780, August 1991.

1990

·         R. Ginosar, Y.Y. Zeevi and O. Hilsenrath, Intelligent Scan Image Sensor, USA Patent 4,942,473, 1990.

1989

·         R. Ginosar and D. Egozi, Topological Comparison of Perfect Shuffle and Hypercube, Int. J. Parallel Programming, 18(1):37-68, 1989.

1988

·         R. Ginosar, Y.Y. Zeevi and O. Hilsenrath, Intelligent Scan Processor, Israel Patent 87,310, 1988.

·         R. Ginosar, O. Hlisenrath, Y.Y. Zeevi, O. Zinaty, D.J. Kligler, Wide Dynamic Range Image Sensor, Israel Patents 87,307/91,095, 1988; European EP431010A1, WO199001844.