Ran Ginosar
|
Associate Professor, Department of Electrical Engineering and Department of Computer Science Head, VLSI Systems Research Center Member, Advanced Circuit Research Center Technion-Israel Institute of Technology Haifa 32000, Israel Office: EE 904 Phone: +972-4-829-4645 Mobile: +972-528-700-580 Fax: +972-4-829-5757 Email: ran at ee.technion.ac.il BSc (scl), Technion, 1978; PhD, EECS, Princeton University, 1982 |
Many-core Plural architecture
Neurochips
VLSI Architecture:
Network-on-Chip and Chip Multi-Processors
Rad-Safe VLSI for Space ApplicationsAsynchronous VLSI:
Synchronization and Multi-Clock Domains (MCD) Systems on Chip (SOC)
The Tutorial [IEEE Design & Test, Sept/Oct 2011]
Asynchronous design
Shlomo Beer (PhD): Advanced Synchronizer Circuits
Efi Rotem (PhD): Multiple Clock Domain Chips (co-advisors Uri Weiser and Avi Mendelson).
Leonid Yavits (PhD): (he still has to decide)
Shimon Manor (MSc): Low Power Multisynchronous Clocking
Danniel Nahmanny (MSc): High Speed Communication Circuits
Itai Avron (MSc): Scheduling in Many-core Architecture
Eyal Nave (MSc): Power Gating and DVFS for IP/TCP Communication SoC
Prarthana Yakov (MSc): Testing of a fast on-chip serial link
Mohamad Nassar (MSc): Parallel Computing Architectures
Ron Diamant (MSc): Low Energy Parallel DSP (co-advisor Rakefet Kol)
Katia Patkin (Tentative MSc): Low Energy Parallel DSP
Dmitry Verbitsky (MSc): Synchronizers
Industrial Involvement and Entrepreneurship
Last Update: 01/02/2012