Academic
Short Bio
I am currently a Ph.D. candidate at the Technion in the department of Electrical Engineering.
1999-2003 I have completed my B.Sc summa cum Laude in Computer Engineering at the Technion, in the department of Electrical engineering.
2001-2003 I have worked at ZORAN for 2 years during my B.Sc. studies. I've been with the logic verification team of the DVD playback department.
Academic areas of interest
- Chip-Multiprocessors (CMP)
- Asymmetric Cluster Chip Multi-Processing (ACCMP)
- Network-on-Chip interconnects (NoC)
Research Advisors
I am very lucky to have 3 top-notch research advisors:
Publications
- Z. Guz, E. Bolotin, I. Keidar, A. Kolodny, A. Mendelson, and U. C. Weiser, "Many-Core vs. Many-Thread Machines: Stay Away From the Valley", IEEE Computer Architecture Letters, April 2009
-
H. Eran, O. Lutzky, Z. Guz, and I. Keidar,
"Transactifying Apache's Cache Module",
SYSTOR 2009 - The Israeli Experimental Systems Conference, May 2009.
talk slides (pdf)
-
Z. Guz, I. Keidar, A. Kolodny, and U. C. Weiser,
"Utilizing Shared Data in Chip Multiprocessors with the Nahalal Architecture",
the 20th ACM Symp. on Parallelism in Algorithms and Architectures(SPAA'08), special track on
Hardware and Software Techniques to Improve the Programmability of Multicore Machines,
pages 1-10, June 2008. talk slides (ppt)
SPAA Best Paper Award - Z. Guz, I. Keidar, A. Kolodny, U. C. Weiser, "Nahalal: Cache Organization for Chip Multiprocessors", IEEE Computer Architecture Letters, vol. 6, no. 1, May 2007
- E. Bolotin, Z. Guz, I. Cidon, R. Ginosar, A. Kolodny, "The Power of Priority: NoC based Distributed Cache Coherency", NOCS 2007
- Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "Network Delays and Link Capacities in Application-Specific Wormhole NoCs", VLSI Design, vol. 2007, Article ID 90941, May 2007
- Z. Guz, I. Keidar, A. Kolodny, U. C. Weiser, "Nahalal: Memory Organization for Chip Multiprocessors", Technical Report CCIT 600, Technion Department of Electrical Engineering, September 2006
- Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, "Efficient Link Capacity and QoS Design for Wormhole Network-on-Chip", DATE, pp. 9-14, March 2006. talk slides (ppt)
Honors and Awards
- The Andrew and Erna Finci Viterbi Fellowship for PhD students, 2009
- Intel Research Excellence Award for graduate students, 2007
- Technion excellence award for teaching assistants, 2007
- Technion excellence award for teaching assistants, 2006
- Technion excellence award for teaching assistants, 2005
- Technion excellence award for enrolled graduate students, 2003
- B.Sc, Summa Cum Laude, Electrical Engineering Department, Technion, 2003
- Best student project, the VLSI System Research Center, Technion, 2003
Current Teaching Positions
- Teaching Assistant at the Microcomputers course (EE-044800)
- Teaching Assistant at the Computer Architecture course (EE-046267)
- Project supervisor at the VLSI System Research Center
-
Project supervisor at the Software System Lab
Motivated students looking for projects for the upcoming semesters (VLSI or software) are encouraged to contact me. (If you have your own idea for a project do drop by, we can define it together.)
Past Teaching Positions
- Teaching Assistant at the VLSI Architecture Design course (EE-048853)
- In charge of the VHDL simulations at the Logic Design course. (EE-044262)
Professional and Technion Activities
- Organizing ClubNet, a networking weekly seminar at the Technion EE department.