I am a Professor at  the Electrical Engineering department at the Technion – Israel Institute of Technology and the head of the CCIT- Irwin and Joan Jacobs Center for Communication and Information Technologies. I am also a board member of TIM (Technion Institute of Management). My research interests are in the fields of converged networks, wireline and wireless network architectures, network algorithms and network on chip.

I got my BSc (summa cum laude) and DsC in Electrical Engineering from the Technion  in 1980 and 1984 respectively.

Industrial R&D

   Between 1985 and 1994, I was a research member and manager of the Network Architecture and Algorithms group at IBM T. J. Watson Research Center, NY, leading projects in high-speed networks and mobile wireless networks. In the late 80s me and my colleagues led the development of the first experimental converged packet based wide area network (PARIS) that integrated data, voice and video and a metropolitan spatial reuse optical ring (MetaRing).  These network technologies were later included in US national Aurora Gigabit testbed (termed plaNET and Orbit) and at the IBM first Storage Area Network (SSA and ANSI X3.293-1996 ). Between 1994 and 1995, I was manager of High-Speed Networking at Sun Microsystems Labs and led  projects in signaling systems and embedded packet switch technology. 

I co-founded Micronet Ltd (founded in 1981), a maker of handheld terminals. I am a co-founder and CTO of  Viola Networks (founded in 1988), a provider of NetAlly - a real-time applications and network performance assurance and diagnostic software.  I was a co-founder and Chief Scientist of Actona Technologies (founded in 2000), a provider of remote office storage centralization solutions. Actona was acquired  by Cisco Systems in August 2004 for $100M.

Other professional details can be found in my CV.

Research Projects

I am involved in several joint projects:

• MaGMA: Mobility and Group Management Architecture. Develop architectures for group management in mobile networks interconnected via IP infrastructure.

• MATRICS: Multiple AsymmeTRic Interconnected Core Systems. Develop methodologies and architectures for microprocessor chips based on multiple asymmetric interconnected cores.

• QNoC: Quality of Service Network on Chip. Research future NOC architectures and design methodologies.