Ilan Spillinger, “Pass Transistor Simulation on a Logic Simulation Machine,” M.Sc. 1984 (graduated with distinction), (long time @IBM, now @Microsoft)
Hagit Zagagy, “Information Flow Control in a Computer System with an Active Memory Unit,” M.Sc. 1984.
Neil Jacobson, “The Simulation Machine,” M.Sc. 1985.
Yehezkel Shifrovitch, “XMP ‑ A Multiprocessor Operating System,” M.Sc. 1985.
Avi Hitelman, “Remote System Call Execution,” M.Sc. 1985.
Avi Schwartz, “The Star Serializing Chip ‑ A Multiprocessor Interconnector,” M.Sc. 1986.
David Egozy, “Comparison of Shuffle Exchange and Hypercube as Parallel Processor Interconnection Networks,” M.Sc. 1986 (@RAFAEL).
Ron Riesenbach, “VLSI System for Real Time Automatic Gain Control Image Processing,” M.Sc. 1986.
Eran Mor, “Taxonomies of Relational Data Base Machines,” M.Sc. 1986.
Eitan Froumine, “A Multiprocessor Operating System to Support High Level Communications and Performance Measurements,” M.Sc. 1987.
Arieh Harsat, “Architecture‑Oriented Execution Analysis of Flat Concurrent Prolog,” M.Sc. 1987 (@Intel)
Yoram Rimoni, “Communication Protocols for a Multicomputer Interconnection Chip,” M.Sc. 1987 (co‑advisor Dr. Uri Weiser) (@QUALCOM)
Ilan Zisman, “Architecture of a Multicomputer Interconnection Chip,” M.Sc. 1987 (co‑advisor Dr. Uri Weiser).
Eran Cohen, “Comparison of VLSI Communication Elements,” M.Sc. 1987.
Gad Grinstein, “Simulation and Performance Evaluation of CARMEL, a Flat Concurrent Prolog Processor,” M.Sc. 1987.
Ricardo Telichevesky, “Intelligent Scan Image Processor,” M.Sc. 1988.
Dov Alon, “A Switch Controller Chip for the MP/C,” M.Sc. 1989 (@RAMON CHIPS).
Nimrod Bayer, “Synchronizer / Scheduler for a Multiprocessor,” M.Sc. 1989 (@PLURALITY)
Alan Rotman, “Control Unit Synthesis from a High Level Language,” M.Sc. 1989.
Avi Nathan, “Compiling Flat Concurrent Prolog to the CARMEL Processor,” M.Sc. 1989 (@Microsoft)
Rami Friedlander, “VLSI Architecture for Morphological Processing of Intelligent Scan Images,” M.Sc. 1989.
Avi Mintz, “VLSI Hough Transform Processor,” M.Sc. 1989.
Shimon Gur, “Investigation of a silicon compiler for the design of CARMEL,” M.Sc. 1989.
Rakefet Kol, “Self Timed Circuits,” M.Sc. 1989 (@ Zoran)
Orly Yadid, “Intelligent Scan Imaging Chip,” M.Sc. (co‑advisor Dr. Yosi Shacham), 1990 (@ BGU).
Ilana David, “Silicon Compilation of Self‑Timed Systems,” D.Sc. (co‑advisor Prof. Michael Yoeli), 1991 (@ Technion)
Arie Harsat, “CARMEL: A Multiprocessor for the Execution of Flat Concurrent Prolog,” D.Sc. 1991 (@ Intel)
Stuart Wolf, “Color Enhancement Algorithm and Architecture,” M.Sc. 1992.
Leonid Yavits, “Architecture of an Associative Image Processor,” M.Sc. 1995.
Sarit Chen, “An Adaptive Sensitivity Sensor,” M.Sc. 1995.
Amir Freizeit, “A Video Compression Algorithm and Architecture,” M.Sc. 1995.
Nitzan Weinberg, “Neural Network VLSI Architecture,” M.Sc. 1995.
Marina Sherman, “An Intelligent Scan Still Image Retrieval Method,” M.Sc. 1996 (@ Intel)
Amir Morad, “Controller for the Adaptive Sensitivity Sensor,” M.Sc. 1998.
Rakefet Kol (PhD 1998): Async Processors (@ Zoran)
Hod Finkelstein (MSc 1998): Electron Detector
Uzi Zangi (MSc 1998): Low Power Processors
Alex Gnusin (MSc 1999): Adaptive Sensitivity CMOS Sensor
Alex Branover (MSc 1999): Desynchronization (@ AMD)
Calist Friedman (MSc 1999): Read-Out IC for QWIP Detectors (@ Nvidia)
Hisham Shafi (MSc 1999): Async Processors (@ Intel)
Yevgeny Perelman (MSc 2000): Low Light Image Sensor (@ Technion)
Yaron Elboim (MSc 2002): Clock Tuning (@ Intel)
Reuven Dobkin (MSc 2003): Decoder Architecture for Convolution Codes (@ vSync & Ramon Chips)
Guy Tamir (MSc 2003): Synchronization (@ Intel)
Yaron Semiat (MSc 2003): Measuring Synchronizers and Multi-Synchronous Synchronization (@ PLDA)
Ilya Obridko (MSc 2005): Minimal Energy Asynchronous Processors (@ Zoran)
Uri Frank (MSc 2005): Predictive Synchronizers (@ Intel)
Tsachy Kapshiz (MSc 2005): Formal Verification of Synchronizers
Alex Zviaguintsev (MSc 2005): Neuroprocessors: VLSI Algorithms for Spike Detection and Sorting (was @ Intel, now @ SCD)
Alexander Lyakhov (MSc 2006): Neuroprocessors: In-Vitro Architecture and Circuit (@ Intel)
Walter Isaschar (MSc 2006): Capacity Allocation and Hot Spots in Netowrk on Chip (@ Intel)
Ziv Yekutieli (MSc 2006): Neuroprocessors: In-Vitro Systems
Michael Tolchinsky (MSc 2006): Measurement of Metastability
Michael Kayam (MSc 2006): Novel Synchronizers (@ Sandisk)
Yevgeny Perelman (PhD 2006): Neuroprocessors (@ Technion)
Evgeny Bolotin (PhD 2007): Network on Chip (@ Intel)
Arkadiy Morgenshtein (PhD 2008): Adaptive Links for Network-on-Chip (@ Intel)
Asaf Baron, (MSc 2008): The Capacity Allocation Paradox
Reuven Dobkin (PhD 2009): Asynchronous Network-on-Chip (@ vSync & Ramon Chips)
Inna Vaisband (MSc 2009): Low Power Clocking (PhD student at U Rochester)
Dmitry Vainbrand (MSc): NoC for Neural Network Processors (@ Intel)
Ameer Abdel-Hadi (MSc 2010): Non-uniform Mesh clocking (PhD student at UBC)
Eyal Friedman (MSc 2011): Processor-to-Memory NoC in Many-core Architecture (@ Intel)
Dmitri Khoretz (MSc 2011): Memory Performance in Many-core Architecture (@ Intel)
Itai Avron (MSc 2012): Scheduling in Many-core Architecture (@ Annapurna Labs)
Eyal Nave (MSc 2013): Power Gating and DVFS for IP/TCP Communication SoC (@ Intel)
Shimon Manor (MSc 2013): Low Power Multisynchronous Clocking (@ Intel)
Danniel Nahmanny (MSc 2013): High Speed Communication Circuits (@ Intel)
Alon Naveh (MSc 2013): Heterogeneous Computer Architecture (@ Intel)
Last Update: 19/04/2016