Tuesday  Wednesday Thursday
 

Tuesday, 4 April 2000

09:00-09:15    Opening session

09:15-10:30    Keynote session I
Avinoam Kolodny, Intel Corporation, Haifa, Israel & Technion--Israel Institute of Technology
Life in the Synchronous Lane (Thoughts About Engineering Methodologies and CAD)

10:30-11:00    Break

11:00-12:30    Session I: Theory & Verification Techniques
Chairperson:  Mark B. Josephs

Formal verification of safety properties in timed circuits, Pena, Cortadella, Pastor, Kondratyev
"On Directed Transformations of Delay Insensitive Specifications, Alternations and Dynamic Nondeterminism,” Mallon
"Composing Snippets,” Benko, Ebergen

12:30-2:30    Lunch

2:30-3:45    Keynote Session II
Professor Shimon Even, Technion--Israel Institute of Technology:
"Retiming: A Technique to Make Systems Run Faster"

3:45-4:15    Break

4:15-5:45    Session II: Asynchronous design in embedded systems
Chairperson:  Peter Beerel

Applying asynchronous circuits in contactless smartcards, Kessels, Besten, Kramer, Timm
“An on-chip dynamically recalibrated delay line for embeddedself-timed systems,” Taylor, Moore, Wilcox, Robinson
Practical Design of Globally-Asynchronous Locally-Synchronous Systems, Muttersbach, Villiger, Fichter

5:45-6:00    Break

6:00-7:30    Panel Session
Mark Greenstreet
"What's your crock?"
Peter Beerel, Al Davis, Luciano Lavagno, Marly Roncken, Jose Tierno, Ken Stevens
 

Wednesday, 5 April 2000

09:00-10:00    Session III: Testability
Chairperson:  Jens Sparsø

CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder, Roncken, Stevens, Roy, Rotem, Pendurkar, Chaudhuri
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits, Shirvani, Mitra, McCluskey, Ebergen, Roncken

10:00-10:30    Break

10:30-12:30    Session IV: Synthesis
Chairperson:  Ken Stevens

Automated synthesis of micro-pipelines from behavioral Verilog HDL, Blunno, Lavagno
High-Level Asynchronous System Design using ACK, Brunvand, Jacobson, Gopalakrishnan
Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis, Kim, Lee, Lee
Asynchronous Design Using Commercial HDL Synthesis Tools, Ligthart, Fant, Smith, Taubin, Kondratyev

12:30-2:30    Lunch

2:30-4:00    Session V: Arbitration & Circuit Techniques
Chairperson:  Tomohiro Yoneda

Priority Arbiters, Bystrov, Yakovlev, Kinniment
Simple Circuits that Work for Complicated Reasons,Molnar, Jones
An asynchronous communication mechanism using self-timed circuits, Xia, Yakovlev, Shang, Bystrov, Koelmans, Kinniment

4:30-7:00    Excursion to Eilat Desert

7:00-10:00    Optional Dinner at the Undersea Restaurant

Thursday, 6 April 2000

9:30-10:30    Session VI: Processor Design
Chairperson:  Doug Edwards

AMULET3i - an Asynchronous System-on-Chip, Garside, Bainbridge, Bardsley, Clark, Furber, Lloyd, Pepper, Temple, Woods
An Instruction Buffer for a Low-Power DSP, Lewis, Brackenbury

10:30-11:00    Break

11:00-12:30    Session VII: Pushing the Performance Limit
Chairperson:  Takashi Nanya

VLSI System Design Using Asynchronous Wave Pipelines: A 0.35um CMOS 1.5GHz Elliptic Curve Public Key Cryptosystem Chip, Hauck, Katoch, Huss
High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths, Singh, Nowick
Low-Latency Asynchronous FIFO's using Token Rings, Chelcea, Nowick

12:30-2:30    Lunch

2:30-4:00    Keynote Session III
Professor Udi Shapiro, Weizmann Isntitute of Science
Abstract Processes Go Live: Representing Biomolecular Processes with Process Algebra

4:00-4:30    Break

4:30-5:30    Award and Closure Session