Isask'har (Zigi) Walter

Department of Electrical Engineering, Techion - Israel Institute of Technology
Advisors: Prof. Israel Cidon and Prof. Avinoam Kolodny
I am a member of the MATRICS (Multiple AssymeTRic Interconnected Core Systems) group


Contacts

E-Mail:   zigi@tx.technion.ac.il


Publications

R. Manevich, I. Cidon, A. Kolodny, I. Walter, and Shmuel Wimer, "A Cost-Effective Centraliized AdaptiveRouting for Networks-on-Chip", the 14th Euromicro Conference on Digital System Design (DSD), 2011

I. Walter, E. Kantor, I. Cidon, and S. Kutten, "Capacity Optimized NoC for Multi-Mode SoC", Design Automation Conference (DAC), 2011

R. Manevich, I. Cidon, A. Kolodny, and I. Walter, "Best of Both Worlds: A Bus Enhanced NoC (BENoC)", IEEEI, 2010

R. Manevich, I. Cidon, A. Kolodny, and I. Walter, "Centralized Adaptive Routing for NoCs",  IEEE Computer Architecture Letters, Volume 9, Issue 2, Feb. 2010

E. Krimer, I. Keslassy, A. Kolodny, I. Walter, and M. Erez, "Static Timing Analysis for Modeling QoS in Networks-on-Chip",  Journal of  Parallel and Distributed Computing, Volume 71, Issue 5, May, 2011

R. Beraha, I. Walter, I. Cidon and A. Kolodny, "Leveraging Application-Level Requirements in The Design of a NoC for a 4G SoC - a Case Study", the Design, Automation and Test in Europe conference (DATE), 2010 [pdf][talk]

I. Walter, I. Cidon,  A. Kolodny, and D. Sigalov, "The Era of Many-Modules SoC: Revisiting the NoC Mapping Problem", the Second International Workshop on Network on Chip Architectures (NoCArc), 2009 [pdf] [talk]

R. Manevich, I. Walter, I. Cidon, and A. Kolodny, "Best of Both Worlds: A Bus Enhanced NoC (BENoC)", ACM/IEEE International Symposium on Networks-on-Chip (NoCs), 2009 [pdf] [talk]

I. Walter, I. Cidon, and A. Kolodny, "BENoC - A Bus-Enhanced Network on-Chip for a Power Efficient CMP", IEEE Computer Architecture Letters, Volume 7, Issue 2, 2008 [pdf]

I. Walter, I. Cidon, R. Ginosar, and A. Kolodny, "Access Regulation to Hot-Modules in Wormhole NoCs", First International Symposium on Networks-on-Chip (NoCs), 2007 [pdf] [talk]

Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, “Network Delays and Link Capacities in Application-Specific Wormhole NoCs”, VLSI Design, vol. 2007, Article ID 90941, 2007 [pdf]

A. Baron, I. Walter, R. Ginosar, and I. Keslassy, "Benchmarking SpaceWire Networks", International SpaceWire Conference, 2007 [pdf] [talk]

A. Baron, I. Walter, I. Cidon, R. Ginosar, and I. Keslassy, "SpaceWire Hot Modules", International SpaceWire Conference, 2007 [pdf] [talk]

Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "Efficient link capacity and QoS design for network-on-chip", Proceedings of the conference on Design, Automation and Test in Europe (DATE), 2006 [pdf] [talk]

Book Chapter:

R. Beraha, I. Walter, I. Cidon, and A. Kolodny, "Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study", Springer, 2010, in press

Other publications:

E. Krimer, I. Keslassy, A. Kolodny, I. Walter, and M. Erez, "Packet-Level Static Timing Analysis for NoCs",  poster, ACM/IEEE Int. Symp. on Networks-on-Chip (NoCs), 2009 [Technical Report]

G. Badishi, A. Bergman, N. Lavi, and I. Walter, "Silent Attack Hindering in Drum", TR CCIT Report #500, Department of Electrical Engineering, Technion, March 2004 [pdf]



Teaching

Microcomputers
Digital Systems
Project supervisor at the High Speed Digital Systems lab, Computer Networks lab,  VLSI lab and Software lab


Project Proposals

Projects for Spring 2009:
High Speed Digital Systems lab [N/A]
VLSI lab [N/A]
Computer Networks lab [N/A]
Software lab [N/A]

Last updated: 23/5/11