Memristors and Memristive Systems  Memristor symbol

Emerging Non-Volatile Memory Technologies (NVM)

 

What is it?

My Research

Memristor Models for SPICE - here you can find code for memristor models for SPICE and MATLAB

Interesting References and Links

Full Reference List

Memristor Conferences and Events

B.Sc. Projects

 

What is it?

Any Electrical Engineering student is familiar with the fundamental passive circuit elements: the resistor, the capacitor and the inductor.

However, in 1971 Leon Chua (a Professor from UC Berkley) reasoned from symmetry arguments that there should be a fourth fundamental element, which he called a memristor (short for memory resistor).

Although he showed that such an element has many interesting and valuable circuit properties, until 2008 no one has presented either a useful physical model or an example of a memristor.

In 2008 HP (Hewlett-Packard) Labs announced that they "succeeded" to fabricate the missing memristor. Since then the interest in this device and its applications is rising and several more memristors were "found" (including RRAM, STT-MRAM, Phase-Change Memory, and spintronics).

The memristor may allow extension of Moore's Law for a few more years.

Memory can be implemented in all levels (cache, main memory and storage) with memristor-based memory and those applications can solve the current leakage problem and be the next generation nonvolatile memory.

There are many other potential applications with memristors including artificial intelligence, analog computing and brain-like circuits, detector of pollution in mobile devices, new approaches for logic and much more.

The memristor and memristive systems research is developing in a fast pace. In the coming graph you can see how fast it is in terms of the number of related published papers each year (according to Google Scholar, updated in 15/09/2015).


If you are interested in memristors and their applications and you want to share ideas and information - contact me.

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My Research about Memristor-based Circuits and Architectures

I am working on memristor-based applications both at circuit and architecture levels.

Right now I am working on several projects - memristor modeling, memristor-based logic design, memristor crossbar design and analysis, and computer architecture in the memristor era (Memory-Intensive Computing).

We organized a workshop on memristors on 7th March, 2012 at the Technion. The program and the presentations can be found here. I talked about "Memristor-based Logic Circuit Design." (my talk). All the lectures are in YouTube.

 

My Publications about Memristors

Book Chapters

N. Wald, E. Amrany, A. Drory, and S. Kvatinsky, "Logic with Unipolar Memristors: Circuits and Design Methodology," VLSI-SoC Book Edition, Springer (in press).     pdf

Refereed Journal Papers

  1. Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "Information-Theoretic Sneak Path Mitigation in Memristor Crossbar Arrays," IEEE Transaction on Information Theory,Vol. 62, No. 9, pp. 4801-4814, September 2016.      pdf
  2. N. Talati, S. Gupta, P. Mane, and S. Kvatinsky, “Logic Design within Memristive Memories Using Memristor Aided loGIC (MAGIC),” IEEE Transactions on NanotechnologyVol. 15, No. 4, pp. 635-650, July 2016.  pdf
  3. A. Morad, L. Yavits, S. Kvatinsky, and R. Ginosar, "Resistive GP-SIMD Processing In-Memory," ACM Transactions on Architecture and Code OptimizationVol. 12, No. 4, Article 57, January 2016.    pdf
  4. L. Yavits, S. Kvatinsky, A. Morad, and R. Ginosar, "Resistive Associative Processor," IEEE Computer Architecture Letters, Vol. 14, No. 2, July-December 2015. Best of CAL winner 2015.     pdf
  5. D. Soudry, D. Di Castro, A. Gal, A. Kolodny, and S. Kvatinsky, "Memristor-based Multilayer Neural Networks with Online Gradient Descent Training," IEEE Transactions on Neural Networks and Learning SystemsVol. 26, No. 10, pp. 2408-2421, October 2015.  pdf       Supplemantary material
  6. R. Patel, S. Kvatinsky, E. G. Friedman, and A. Kolodny, "Multistate Register Based on Resistive RAM," IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 23, No. 9, pp. 1750-1759, September 2015.  pdf
  7. S. Kvatinsky, M. Ramadan, E. G. Friedman, and A. Kolodny, "VTEAM – A General Model for Voltage Controlled Memristor," Transactions on Circuits and Systems II: Express Briefs, Vol. 62, No. 8, pp. 786-790, August 2015pdf
  8. Y. Levy, J. Bruk, Y. Cassuto, E. G. Friedman, A. Kolodny, E. Yaacobi, and S. Kvatinsky, "Logic Operation in Memory Using a Memristive Akers Array," Microelectronics Journal, Vol. 45, No. 11, pp. 1429-1437, November 2014. pdf 
  9. S. Kvatinsky, D. Belousov, S. Liman, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, and U. C. Weiser, "MAGIC – Memristor Aided LoGIC," IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61, No. 11, pp. 1-5, November 2014. pdf
  10. S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-based Material Implication (IMPLY) Logic: Design Principles and Methodologies," IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 22, No. 10, pp. 2054-2066, October 2014. pdf
  11. S. Kvatinsky, Y. H. Nacson, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-based Multithreading,"  IEEE Computer Architecture Letters, Vol. 13, No. 1, pp. 41-44, January-June 2014. pdf
  12. S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "TEAM - ThrEshold Adaptive Memristor Model," IEEE Transactions on Circuits and Systems I: Regular Paper, Vol. 60, No. 1, pp. 211-221, January 2013. 2015 Guillemin-Cauer Best Paper Award. pdf

Refereed Conference Papers

  1.  N. Wainsten and S. Kvatinsky, "An RF Memristor Model and Memristive Single-Pole Double-Throw Switches," Proceeding of the IEEE International Conference on Circuits and Systems, May 2017 (in press).     pdf
  2. N. Talati, Z. Wang, and S. Kvatinsky, "Rate-Compatible and High-Throughput Architecture Designs for Encoding LDPC Codes," Proceeding of the IEEE International Conference on Circuits and Systems, May 2017 (in press).    pdf
  3. L. Azriel and S. Kvatinsky, "Towards a Memristive Hardware Secure Hash Function (MemHash)", Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2017 (in press).    pdf
  4. R. Ben-Hur and S. Kvatinsky, "Memristive Memory Processing Unit (MPU) Controller for In-Memory Processing", Proceedings of the IEEE International Conference on Science of Electrical Engineering, November 2016.   pdf
  5. S. Kvatinsky, R. Ben-Hur, N. Talati, and N. Wald, "mMPU: Memristive Memory Processing Unit," International Conference on Memristive Materials, Devices & Systems, April 2017.
  6.  S. Hamdioui, S. Kvatinsky, G. Cauwenberghs, L. Xie, K. Bertels, N. Wald, S. Joshi, H. M. Elsayed, and H. Corporaal, "Memristor For Computing: Myth or Reality?" Proceedings of the Design, Automation and Testing in Europe, pp. 722-731, March 2017.  pdf
  7. N. Wald and S. Kvatinsky, "Design Methodology for Stateful Memristive Logic Gates", Proceedings of the IEEE International Conference on Science of Electrical Engineering, November 2016 (in press).    pdf
  8. E. Amrany, A. Drory, and S. Kvatinsky, "Logic Design with Unipolar Memristors," Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), September 2016 (in press).    pdf
  9. R. Ben-Hur, N. Talati, and S. Kvatinsky, "Algorithmic Considerations in Memristive Memory Processing Units (MPU)," Proceedings of the International Cellular Nanoscale Networks and their Applications, August 2016 (in press).  pdf
  10.  R. Ben-Hur and S. Kvatinsky, "Memory Processing Unit for In-Memory Processing," Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, July 2016 (in press).   pdf
  11. Y. Cassuto, S. Kvatinsky, and E. Yaakobi, “Write Sneak-Path Constraints Avoiding Disturbs in Memristor Crossbar Arrays,” Proceedings of the IEEE International Symposium on Information Theory  2016 (in press).  pdf
  12. S. Greshnikov, E. Rosenthal, D. Soudry, and S. Kvatinsky, “A Fully Analog Memristor-Based Multilayer Neural Network with Online Backpropagation Training,” Proceeding of the IEEE International Conference on Circuits and Systems, pp. 1394-1397, May 2016pdf
  13. M. Ramadan, S. Kvatinsky, and R. Ginosar, "Memristor Modeling," Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016.
  14. L. Danial and S. Kvatinsky, "Memristive Artificial Neural Networks Based Analog to Digital Converter (ADC), Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016.
  15. R. Ben-Hur and S. Kvatinsky, "Processing within a Memristive Memory," Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016.
  16. Z. Jiang, P. Huang, L. Zhao, S. Kvatinsky, S. Yu, X. Liu, J. Kang, Y. Nishi, and H.-S. P. Wong, “Analysis and Predication on Resistive Random Access Memory (RRAM) 1S1R Array,” Proceedings of the 2015 International Memory Workshop, pp. 1-4, May 2015. pdf
  17. S. Kvatinsky, Y. H. Nacson, R. Patel, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristive Multistate Pipeline Register," Proceedings of the International Cellular Nanoscale Networks and their Applications, pp. 1-2, July 2014. pdf
  18. Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "On the Channel Induced by Sneak-Path Errors in Memristor Arrays," Proceedings of the International Conference on Signal Processing and Communication, pp. 1-6, July 2014. pdf
  19. S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memory Intensive Computing," Proceeding of the Annual Non-Volatile Memories Workshop, March 2014.
  20. Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "Sneak-Path Constraints in Memristor Crossbar Arrays," Proceedings of the IEEE International Symposium on Information Theory, pp. 156-160, July 2013. pdf
  21. Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "Sneak-Path Constraints in Memristor Crossbar Arrays," Proceeding of the Annual Non-Volatile Memories Workshop, March 2013.
  22. S. Kvatinsky, K. Talisveyberg. D. Fliter, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Models of Memristors for SPICE Simulations," Proceedings of the IEEE Convention of Electrical and Electronics Engineers in Israel, pp. 1-5, November 2012. pdf
  23. S. Kvatinsky, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, and U. C. Weiser, "MRL - Memristor Ratioed Logic," Proceedings of the International Cellular Nanoscale Networks and their Applications, pp. 1-6, August 2012. pdf   presentation
  24. S. Kvatinsky, E.G. Friedman, A. Kolodny, and U.C. Weiser, "Memristor-based IMPLY Logic Design Procedure," Proceedings of the IEEE 29th International Conference on Computer Design, pp.142-147, October 2011. pdf    presentation

Technical Reports

  1. S. Kvatinsky, E.G. Friedman, A. Kolodny, and U.C. Weiser, "Memristor-based IMPLY Logic Design Procedure," CCIT Technical Report #795, August 2011.
  2. S. Kvatinsky, K. Talisveyberg, D. Fliter, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Verilog-A for Memristor Models," CCIT Technical Report #801, December 2011. pdf
  3. S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "TEAM - ThrEshold Adaptive Memristor Model," CCIT Technical Report #804, January 2012. pdf
  4. D. Soudry, D. Di Castro, A. Gal, A. Kolodny, and S. Kvatinsky, "Memristor-based Multilayer Neural Networks with Online Gradient Descent Training," CCIT Technical Report #840, September 2013. 
  5. S. Kvatinsky, M. Ramadan, E. G. Friedman, and A. Kolodny, "VTEAM - A General Model for Voltage Controlled Memristors," CCIT Technical Report #856, April 2014.  pdf
  6. R. Ben Hur, N. Wald, N. Talati, and S. Kvatinsky, " Latency Optimized Mapping of Logic Functions for Memristor Aided Logic (MAGIC)," CCIT Technical Report #908, December 2016.   pdf

 
Magazines

S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "The Desired Memristor for Circuit Designers," IEEE Circuits and Systems Magazine, second quarter, Vol. 13, No. 2, pp. 17-22, second quarter 2013. pdf

 

Selected Talks on Memristors

S. Kvatinsky, E. G. Friedman, A. Kolodny and U.C. Weiser, "Memristors and Related Applications," The International Conference of the Israeli Semiconductor Industry (ChipEx 2011), May 2011.

S. Kvatinsky, "Memristor-based Logic Circuit Design," IEEE/ACRC Workshop on Memristors and Resistive Memory: Devices and Applications, March 2012. Presentation        YouTube

S. Kvatinsky,   E. G. Friedman, A. Kolodny and U.C. Weiser, "The Desired Memristor for Circuit Designers," Nature Conference on Frontiers in Electronic Materials, June 2012. Presentation    Abstract

S. Kvatinsky,  "Memristors - Not Just Memory," The Annual Conference of the Israeli Semiconductor Industry (ChipEx 2013), May 2013.       Presentation         Best Lecture Award.

S. Kvatinsky, "Building the Computers of the Future - A Talk about Resistors, Memory, and More," Jacobs Showcase Lecture Series: Much is New Under the Sun, Technion - Israel Institute of Technology, Haifa, Israel, November 2013.  Presentation    Abstract    Poster

S. Kvatinsky, "Memory Intensive Computing," HiPEAC 2014, Vienna, Austria, January 2014.      Presentation

S. Kvatinsky, "Memory Intensive Computing," DATE 2014, Dresden, Germany, March 2014.

 

Memristor B.Sc. Projects

 

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Interesting References and Links about Memristors

Here are some interesting and basic links about memristors. Those links are good for a start.

Memristors on Wikipedia.

Memristor website:  http://www.memristor.org/

Chua's original paper on memristors. pdf

HP's paper about "the missing memristor found". pdf

Overview on STT-MRAM. pdf

A paper about memristor-based memory. pdf

Interesting presentations from IEDM 2011.     HP      Wasser

ACRC workshop in the Technion, March 2012 schedule and presentations

 

Full Reference List

In this link you can find many papers that I read and found interesting.

 

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Conferences with memristors sessions

In this section, I publish conferences about memristors, conferences with sessions about memristors or conferences with interesting presentations about memristors.

You are welcome to send me details about coming relevant conferences that you are familiar with.

Seiden Workshop on "Beyond CMOS: from Devices to Systems", 5-6 June 2017, Technion, Haifa, Israel.

MemTDAC 2016, 20th January 2016, Prague, Czech Republic.

MemTDAC 2015, 2015, Amsterdam, Holland.

2014 Fourth Memristor and Memristive Symposium and CNNA 2014, 28th July 2014, Notre Dame, IN, USA.

DATE 2014, special workshop on "Memristor Science and Technology," 28th March 2014, Dresden, Germany.

MemTDAC 2014, 22nd January, 2014, Vienna, Austria.

ICECS 2013, special session about memristors, 8-11 December 2013, Abu Dhabi, UAE.

Workshop on “Memristor-based Systems for Neuromorphic Applications”, September 16-17, 2013, Torino, Italy.

"Non-Volatile Emerging Memories" Colloquium , June 7th, 2013, Nantes, France.

MemCo Workshop, "Memristors for Computing", 19-21 November 2012, Frejus, France.

2nd International Workshop on Resistive RAM, 8-9 October 2012, Stanford, CA, USA.

ICNAAM 2012, Kos, Greece, 19-25 September, 2012 - hold a symposium on "Memristor-based Neuromorphic Circuits and Unconventional Computing."

2012 Third Memristor and Memristive Systems Symposium and CNNA 2012, 28-31 August 2012, Turin, Italy - holds a special symposium and three special sessions.

Nature Conference, Frontiers in Electronic Materials: Correlation Effects and Memristive Phenomena, June 17-20, 2012, Eurogress Aachen, Aachen, Germany.

ISCAS 2012, Seoul, South Korea, 20-23 May, 2012 - holds a session on "Memristors and Memristive Systems."

ACRC Workshop on memristors and resistive memory, 7th March, 2012, Technion, Haifa, Israel.

ICCD 2011, Amherst, Massachusetts, 10-13 October, 2011 - holds a session about memristors.

Flash Memory Summit 2011, Santa Clara, California, 8-11 August, 2011 - holds a session about RRAM.

ICIC 2011, Zhengzhou, Henan Province, China, August 11-14, 2011 - holds a special session on 'Modeling, Theory and Application of Memristor-based Systems'.

ICECS 2010, Athens, Greece, December 12-15, 2010 - holds a session on 'Memristive Devices and Applications'.

ISCAS 2010, Paris, France, May 30th - June 2nd, 2010 - holds two sessions - 'Memristors and Memristive Systems – From Devices to Applications', and 'Memristor Fabrication/Experimentation'.

DATE 2010, Dresden, Germany, March 8-12, 2010 - holds a session on 'Memristor: Device, Design and Application'.

2010 Second Memristor and Memristive Systems Symposium, UC Berkeley, February 2-4, 2010 - the link follows to the video of the conference.

2008 First Memristor and Memristive Systems Symposium, UC Berkeley, November 21st, 2008 - the link follows to the video of the conference.

 

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