Shahar Kvatinsky

שחר קוטינסקי

Shahar 

 

 

 

Contact       Personal        Teaching         CV        Memristors

 

I am an assistant professor at the department of electrical engineering at the Technion - Israel Institute of Technology.

Before coming to the Technion, I was a post doctoral research fellow at the computer science department, Stanford University, working with Prof. Mark Horowitz.

 

Research Interests

Circuit design

Computer architecture

Power distribution networks

VLSI systems

Chip Multiprocessor (CMP)

Multithreading

Energy efficiency in computers

Memory, especially emerging non-volatile memory technologies (STT-MRAM, PCM, RRAM, Memristors, 3D Xpoint, CBRAM, etc.)

Hardware security

Neuromorphic computing

 

Research Projects

Ongoing

Memristor-based circuits, memristor-based architectures.

Energy efficient architectures. 

Retired

Optical Bio Sensor of Hazards in Sources of Water (won best project award for computer engineering and applied physics in the Hebrew University of Jerusalem 2009).

Design and analysis of power distribution networks.

 

Updates

 

Book Chapters

N. Wald, E. Amrany, A. Drory, and S. Kvatinsky, "Logic with Unipolar Memristors: Circuits and Design Methodology," VLSI-SoC Book Edition, Springer (in press).     pdf

Refereed Journal Papers

  1. A. Doz, I. Goldstein, and S. Kvatinsky, "Analysis of the Row Grounding Method in a Memristor-Based Crossbar Array," (submitted)
  2. R. Patel, S. Kvatinsky, and E. G. Friedman, "STT-MRAM Based Multistate Register," (submitted).
  3. Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "Information-Theoretic Sneak Path Mitigation in Memristor Crossbar Arrays," IEEE Transaction on Information Theory, Vol. 62, No. 9, pp. 4801-4814, September 2016.      pdf
  4. N. Talati, S. Gupta, P. Mane, and S. Kvatinsky, “Logic Design within Memristive Memories Using Memristor Aided loGIC (MAGIC),”IEEE Transactions on NanotechnologyVol. 15, No. 4, pp. 635-650, July 2016.    pdf
  5. A. Morad, L. Yavits, S. Kvatinsky, and R. Ginosar, "Resistive GP-SIMD Processing In-Memory," ACM Transactions on Architecture and Code OptimizationVol. 12, No. 4, Article 57, January 2016.    pdf
  6. L. Yavits, S. Kvatinsky, A. Morad, and R. Ginosar, "Resistive Associative Processor," IEEE Computer Architecture Letters, Vol. 14, No. 2, July-December 2015. Best of CAL winner 2015.     pdf
  7. D. Soudry, D. Di Castro, A. Gal, A. Kolodny, and S. Kvatinsky, "Memristor-based Multilayer Neural Networks with Online Gradient Descent Training," IEEE Transactions on Neural Networks and Learning SystemsVol. 26, No. 10, pp. 2408-2421, October 2015.    pdf
  8. R. Patel, S. Kvatinsky, E. G. Friedman, and A. Kolodny, "Multistate Register Based on Resistive RAM," IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 23, No. 9, pp. 1750-1759, September 2015.  pdf
  9. S. Kvatinsky, M. Ramadan, E. G. Friedman, and A. Kolodny, "VTEAM – A General Model for Voltage Controlled Memristor," Transactions on Circuits and Systems II: Express Briefs, Vol. 62, No. 8, pp. 786-790, August 2015pdf
  10. Y. Levy, J. Bruk, Y. Cassuto, E. G. Friedman, A. Kolodny, E. Yaacobi, and S. Kvatinsky, "Logic Operation in Memory Using a Memristive Akers Array," Microelectronics Journal, Vol. 45, No. 11, pp. 1429-1437, November 2014. pdf 
  11. S. Kvatinsky, D. Belousov, S. Liman, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, and U. C. Weiser, "MAGIC – Memristor Aided LoGIC," IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61, No. 11, pp. 1-5, November 2014. pdf
  12. S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-based Material Implication (IMPLY) Logic: Design Principles and Methodologies," IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 22, No. 10, pp. 2054-2066, October 2014. pdf
  13. S. Kvatinsky, Y. H. Nacson, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-based Multithreading,"  IEEE Computer Architecture Letters, Vol. 13, No. 1, pp. 41-44, January-June 2014. pdf
  14. S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "TEAM - ThrEshold Adaptive Memristor Model," IEEE Transactions on Circuits and Systems I: Regular Paper, Vol. 60, No. 1, pp. 211-221, January 2013. 2015 Guillemin-Cauer Best Paper Award. pdf

Refereed Conference Papers

  1. L. Azriel and S. Kvatinsky, "Towards a Memristive Hardware Secure Hash Function (MemHash)", Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2017 (in press).    pdf
  2.  N. Wainsten and S. Kvatinsky, "A Lumped RF Memristor Model and Memristive Single-Pole Double Throw Switches," Proceeding of the IEEE International Conference on Circuits and Systems, May 2017 (in press).
  3. N. Talati, Z. Wang, and S. Kvatinsky, "Rate-Compatible and High-Throughput Architecture Designs for Encoding LDPC Codes," Proceeding of the IEEE International Conference on Circuits and Systems, May 2017 (in press).
  4. R. Ben-Hur and S. Kvatinsky, "Memristive Memory Processing Unit (MPU) Controller for In-Memory Processing", Proceedings of the IEEE International Conference on Science of Electrical Engineering, November 2016.   pdf
  5. N. Wald and S. Kvatinsky, "Design Methodology for Stateful Memristive Logic Gates", Proceedings of the IEEE International Conference on Science of Electrical Engineering, November 2016.    pdf
  6. H. Ha, A. Pedram, S. Richardson, S. Kvatinsky, and M. Horowitz, “Improving Energy Efficiency of DRAM by Exploiting Half Page Row Access,” Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, pp. 1-12, October 2016pdf
  7. A. Vasilyev, N. Bhagdikar, S. Richardson, A. Pedram, S. Kvatinsky, and M. Horowitz, “Evaluating Programmable Architectures for Image and Vision Applications,”  Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, pp. 1-13, October 2016.   pdf
  8. E. Amrany, A. Drory, and S. Kvatinsky, "Logic Design with Unipolar Memristors," Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), September 2016 (in press).    pdf
  9. R. Ben-Hur, N. Talati, and S. Kvatinsky, "Algorithmic Considerations in Memristive Memory Processing Units (MPU)," Proceedings of the International Cellular Nanoscale Networks and their Applications, August 2016 (in press).  pdf
  10.  R. Ben-Hur and S. Kvatinsky, "Memory Processing Unit for In-Memory Processing," Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, July 2016 (in press).   pdf
  11. Y. Cassuto, S. Kvatinsky, and E. Yaakobi, “Write Sneak-Path Constraints Avoiding Disturbs in Memristor Crossbar Arrays,” Proceedings of the IEEE International Symposium on Information Theory  2016 (in press).  pdf
  12. S. Greshnikov, E. Rosenthal, D. Soudry, and S. Kvatinsky, “A Fully Analog Memristor-Based Multilayer Neural Network with Online Backpropagation Training,” Proceeding of the IEEE International Conference on Circuits and Systems, pp. 1394-1397, May 2016pdf
  13. M. Ramadan, S. Kvatinsky, and R. Ginosar, "Memristor Modeling," Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016.
  14. L. Danial and S. Kvatinsky, "Memristive Artificial Neural Networks Based Analog to Digital Converter (ADC), Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016.
  15. R. Ben-Hur and S. Kvatinsky, "Processing within a Memristive Memory," Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016.
  16. Z. Jiang, P. Huang, L. Zhao, S. Kvatinsky, S. Yu, X. Liu, J. Kang, Y. Nishi, and H.-S. P. Wong, “Analysis and Predication on Resistive Random Access Memory (RRAM) 1S1R Array,” Proceedings of the 2015 International Memory Workshop, pp. 1-4, May 2015. pdf
  17. S. Kvatinsky, Y. H. Nacson, R. Patel, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristive Multistate Pipeline Register," Proceedings of the International Cellular Nanoscale Networks and their Applications, pp. 1-2, July 2014. pdf
  18. Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "On the Channel Induced by Sneak-Path Errors in Memristor Arrays," Proceedings of the International Conference on Signal Processing and Communication, pp. 1-6, July 2014. pdf
  19. S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memory Intensive Computing," Proceeding of the Annual Non-Volatile Memories Workshop, March 2014.
  20. Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "Sneak-Path Constraints in Memristor Crossbar Arrays," Proceedings of the IEEE International Symposium on Information Theory, pp. 156-160, July 2013. pdf
  21. Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "Sneak-Path Constraints in Memristor Crossbar Arrays," Proceeding of the Annual Non-Volatile Memories Workshop, March 2013.
  22. S. Kvatinsky, K. Talisveyberg. D. Fliter, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Models of Memristors for SPICE Simulations," Proceedings of the IEEE Convention of Electrical and Electronics Engineers in Israel, pp. 1-5, November 2012. pdf
  23. S. Kvatinsky, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, and U. C. Weiser, "MRL - Memristor Ratioed Logic," Proceedings of the International Cellular Nanoscale Networks and their Applications, pp. 1-6, August 2012. pdf   presentation
  24. S. Kvatinsky, E.G. Friedman, A. Kolodny, and U.C. Weiser, "Memristor-based IMPLY Logic Design Procedure," Proceedings of the IEEE 29th International Conference on Computer Design, pp.142-147, October 2011. pdf    presentation
  25. S. Kvatinsky, E. G. Friedman , A. Kolodny, and  L. Schächter, "Power Grid Analysis Based on a Macro Circuits Model", Proceedings of the IEEE 26th Convention of Electrical and Electronics Engineers in Israel, pp. 708-712,  November 2010.  pdf      presentation

Technical Reports

  1. S. Kvatinsky, E.G. Friedman, A. Kolodny, and U.C. Weiser, "Memristor-based IMPLY Logic Design Procedure," CCIT Technical Report #795, August 2011.
  2. S. Kvatinsky, K. Talisveyberg, D. Fliter, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Verilog-A for Memristor Models," CCIT Technical Report #801, December 2011. pdf
  3. S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "TEAM - ThrEshold Adaptive Memristor Model," CCIT Technical Report #804, January 2012. pdf
  4. D. Soudry, D. Di Castro, A. Gal, A. Kolodny, and S. Kvatinsky, "Memristor-based Multilayer Neural Networks with Online Gradient Descent Training," CCIT Technical Report #840, September 2013. 
  5. S. Kvatinsky, M. Ramadan, E. G. Friedman, and A. Kolodny, "VTEAM - A General Model for Voltage Controlled Memristors," CCIT Technical Report #856, April 2014.  pdf
  6. R. Ben Hur, N. Wald, N. Talati, and S. Kvatinsky, " Latency Optimized Mapping of Logic Functions for Memristor Aided Logic (MAGIC)," CCIT Technical Report #908, December 2016.

 Magazines

  1. A. Pedram, S. Richardson, S. Galal, S. Kvatinsky, and M. Horowitz, “Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era”, IEEE Design and Test, arXiv:1602.04183,  (in press).  pdf

  2. S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "The Desired Memristor for Circuit Designers," IEEE Circuits and Systems Magazine, second quarter, Vol. 13, No. 2, pp. 17-22, second quarter 2013. pdf

 Patents

  1. D. Soudry, S. Kvatinsky, A. Gal, D. Di Castro, and A. Kolodny, "Analog Multiplier Using Memristor a Memristive Device and Methods for Implementing Hebbian Learning Rules Using Memristor Arrays," US patent application no. 61/804,671.
  2. S. Kvatinsky, A. Kolodny, and U. C. Weiser, "Memristor-Based Multithreading," Israel patent application no. 225988.
  3. S. Kvatinsky, A. Kolodny, and U. C. Weiser, "Memristor-Based Multithreading," US patent application no. 14/219,030.
  4. S. Kvatinsky, A. Kolodny, R. Patel, and E. G. Friedman, "ReRAM-Based Multistate Register," US patent application no. 61/940,499.
  5. S. Kvatinsky, D. Belousov, S. Liman, and G. Satat, "Memristor Aided Logic," US patent application no. 61/950,114.
  6. S. Kvatinsky, Y. Levy, and A. Kolodny, "Akers Logic Array with Memristive Devices," US patent no. 9,548,741.
  7. A. Morad, L. Yavits, S. Kvatinsky, and R. Ginosar, “A Hybrid Processor,” US patent application no. 62/100,967.
  8. A. Drori, E. Amrani, and S. Kvatinsky, "Implementation of Logic Circuits with Unipolar Memristive Devices, Thin Film Resistive Switches, and Phase Change Memory," US patent application no. 62/340,559. 
  9.  M. Ramadan, S. Kvatinsky, and R. Ginosar, "Adaptive Programming for Memories with Multi-Level Cells," US patent application no. 62/432,615.

Selected Talks

S. Kvatinsky,   E. G. Friedman, A. Kolodny and U.C. Weiser, "Memristors and Related Applications," The International Conference of the Israeli Semiconductor Industry (ChipEx 2011), May 2011.

S. Kvatinsky, "Memristor-based Logic Circuit Design," IEEE/ACRC Workshop on Memristors and Resistive Memory: Devices and Applications, March 2012. Presentation        Youtube

S. Kvatinsky,   E. G. Friedman, A. Kolodny and U.C. Weiser, "The Desired Memristor for Circuit Designers," Nature Conference on Frontiers in Electronic Materials, June 2012. Presentation    Abstract

S. Kvatinsky,  "Memristors - Not Just Memory," The Annual Conference of the Israeli Semiconductor Industry (ChipEx 2013), May 2013.       Presentation         Best Lecture Award.

S. Kvatinsky, "Building the Computers of the Future - A Talk about Resistors, Memory, and More," Jacobs Showcase Lecture Series: Much is New Under the Sun, Technion - Israel Institute of Technology, Haifa, Israel, November 2013.  Presentation    Abstract    Poster

S. Kvatinsky, "Memory Intensive Computing," HiPEAC 2014, Vienna, Austria, January 2014.      Presentation

 

Last Updated: 16/3/2017

 

 

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