Avinoam Kolodny

 אבינעם קולודני






Department of Electrical Engineering  
VLSI Systems Research Center
Technion-Israel Institute of Technology 
Haifa 32000, Israel 
Office: EE 809 
Phone: +972-4-829-4764  
Fax: +972-4-832-3041 
Email: kolodny@ee.technion.ac.il

BSc 1975; MSc 1977, DSc 1980, Technion

 

Publications    Courses   Presentations

Teaching statement

CV


Research

Electronic Design Automation; Device, circuit and system modeling; Circuit design techniques; Engineering methodologies; 
Algorithms and software for analysis and synthesis of VLSI systems;  VLSI architecture; VLSI interconnect; Networks on Chip.

Network-on-Chip
IEEE International NoC Symposium
MATRICS: Multiple AsymmeTRic Interconnected Core Systems
Memristors
 

Graduate students     

        D. Sc. 

Evgeny Bolotin ,  "Network On Chip", (With I. Cidon (principal supervisor after conversion to direct PhD track) and R. Ginosar).
Graduated: 2007; Currently at Intel’s microprocessor architecture group.

 Arkadiy Morgenstein, "Links for Network-on-Chip", (With R. Ginosar (principal supervisor)).
Graduated: 2008; Currently at Intel’s Design Technology group.

Tomer Morad, "Asymmetric Clustered Chip Multiprocessors", (With U. Weiser).

 Konstantin Moiseev, "CMOS layout migration automation", (With S. Wimer).

 Reuven Dobkin, “High speed asynchronous communication for SoC” (With R. Ginosar (principal supervisor)).
Graduated: 2009.

Zigi Walter, Network on Chip for CMP (with I. Cidon (principal supervisor)).

 Zvika Guz ,"Cache organization for chip multiprocessors",
(With Dr. U. Weiser (principal supervisor)  and Dr. I. Keidar)

Michael Sotman, "Allocation of metal resources in chip interconnect", (with Prof. E. Friedman).

Ran Manevich, "Bus enhanced Network on Chip" (with I. Cidon (principal supervisor)).

Yaniv Ben-Izhak, (with I. Cidon (principal supervisor)).

Eitan Zahavi, “Lossless networks in and out of the chip”  (with I. Cidon).

Shahar Kvatinsky, “Memristor-based circuits and architectures” (with E. Friedman and U. Weiser).


   

M.Sc.  

Yaron Elboim, "Clocking issues in System-On-Chip design", (With Dr. R. Ginosar).
 Graduated: 2001; Currently with Wilocity.

Noam Dolev, "Integrated low-voltage delta-sigma conversion circuits in digital  CMOS  Technology".
Graduated: 2002; Currently a Ph.D. student at Stanford.

Oleg Milter, "Synthesis of CMOS VLSI circuits considering digital noise effects".
Graduated: 2002; Currently logic synthesis team leader in the mobile processors division at Intel.

Georgy Schupak, "High-speed, low-power medium-size cache design".
Graduated: 2002; Currently design team leader at Intel’s mobile processors division.

Oleg Kosyakovsky, "Approaches to managing Trace Cache in computer systems",
 (With Dr. A. Mendelson (principal supervisor)).
Graduated: 2002; Currently a software engineer at Intel.

Nir Magen, "Power Issues in VLSI Interconnect",  (With Dr. U. Weiser).
Graduated: 2003; Joined Intel after graduation. Died in a road accident in 2005.

Assad  Khamaisee, "Combining trace cache and value prediction",  (With Dr. A. Mendelson (principal supervisor)).
Graduated: 2003; Currently with Mellanox.

Michael Moreinis, "Repeater insertion in deep submicron VLSI circuits".
Graduated: 2004; Currently a circuit designer at Intel.

Tomer Morad, "Data trace cache",  (With Dr. U. Weiser (principal supervisor)).
Graduated: 2005; Currently with Horizon semiconductor and a PhD student.

Shay Michaely, "Wiring modifications for optimal migration of processors", 2005.  (With Dr. S. Wimer).
Grduated: 2005; Currently with Avnet ASIC.

Konstantin Moiseev, "Performance optimization by wire reordering",  (With Dr. S. Wimer).
Graduated: 2005; Currently a full-time PhD student.

Walter Isaskhar, "Functional interfaces for Network-On-Chip",   (With Prof. I. Cidon (principal supervisor) and Dr. R. Ginosar).
Graduated: 2005; Currently a full-time PhD student.

Michael Behar, "Hot traces in modern processors", (With Dr. A. Mendelson (principal supervisor)).
Graduated: 2005; Currently at Intel’s microprocessor architecture research group.

Anastasia Barger, "Modeling and design of Network-on-Chip interconnects".
Graduated: 2006; Currently with IBM.

Michael Sotman, "Power delivery structures in VLSI".
Graduated: 2006; returned as PhD student in 2009..

Dror Barash, "Cache Manipulations to Improve Multimedia Applications", (with U. Weiser (principal supervisor)).
Graduated: 2007;

Iris Sorani, Long Instruction Traces and their Usage", (with A. Mendelson (principal supervisor)).
Graduated: 2007; currently with Intel.

Evgeny Krimer, "Evaluation and Optimization of Transmission Latencies in a
 Network-On-Chip", (with Dr. I. Kelassy (principal supervisor)).
Graduated: 2009; currently a PhD student at UT Austin.

Chen Damishian, "Improving cache management policy by identifying repeated sequences of accesses", (with Dr. A. Mendelson (principal supervisor)).
Graduated: 2009; currently with Intel.

Yaniv Ben-Izhak, "Performance and Power Aware Threads Allocation for NoC CMP", (with I. Cidon (principal supervisor)).
Graduated: 2009. Currently a PhD candidate.

Inna Vaisband, “Low Power Clocking,” (with E. Friedman and R. Ginosar (principal supervisor)).
Graduated: 2009; currently a PhD student at U. Rochester.

Yoni Aizik, “Design Considerations for Low Power CMOS Digital Circuits”.
Graduated: 2009; currently with Intel.

Shmuel Zobel, |"Performance-power tradeoffs in General Purpose Graphics Processors," (with A. Mendelson (principal supervisor)).
Graduated: 2010; currently with Intel.

Ameer Abdel-Hadi, “Non-uniform Mesh clocking,” M.Sc. (with E. Friedman and R. Ginosar).
Graduated: 2010; currently a PhD student at UBC.

Anna Kouslik, "Power Macro-modeling in VLSI design ".
Graduated: 2010; currently with Intel.               

Gregory Sizikov, "Design and Analysis of Integrated Voltage Regulators," (with E. Friedman).
Graduated: 2011; currently with Intel.

Yaron Cohen, "Low Power D/A Converter Design Considerations," (with R. Ginosar (principal supervisor)).

Victoria Vishnyakov, "Inductive effects in on-chip interconnect," (with E. Friedman).
Graduated: 2011; currently with Intel.               

Amnon Stanislavsky, "Power-driven floorplanning", (with S. Wimer).

Roman Malits, "Novel thread scheduling in GPGPU", (with A. Mendelson (principal supervisor)).
Graduated: 2010; currently with Rafael.               


 


            

Publications

 Journal Papers

  1. J.   Shappir  and  A.Kolodny,  "The  Response  of  Small Photovoltaic  Detectors  to Uniform Radiation,” IEEE Transactions  on  Electron Devices, Vol. ED-24, pp.1093-1098, 1977. pdf

  2. T.   Bernstein  and  A. Kolodny,  "A  Useful  Method  for Approximating  the  Profile  of  Ions  Implanted through a Thin  Film,”  IEEE  Trans. on  Electron   Devices,   Vol. ED-24, pp.1365-1366, 1977. pdf

  3. A.  Kolodny  and  J. Shappir,  "Diffusion  Properties  of Cadmium  in InSb,” Journal of the Electrochemical Society, Vol.125, no. 9, pp.1530-1534, 1978. pdf

  4. A.  Kolodny,  "Current  Gain  of  Shallow-Junction  Lateral  Transistors,”  IEEE  Transactions  on Electron Devices, Vol.  ED-26,  pp.987-989, 1979. pdf

  5. A.  Kolodny and I.  Kidron,  "Properties  of  Ion-Implanted  Junctions   in   Mercury-Cadmium-Telluride,”  IEEE  Transactions  on  Electron Devices, Vol.  ED-27, pp.37-43, 1980. pdf

  6. A.   Kolodny,  Y.J.    Shacham-Diamand   and  I. Kidron, "N-Channel  MOS Transistors in Mercury-Cadmium-Telluride,” IEEE Transactions  on Electron Devices, Vol.  ED-27, pp.591-595, 1980. pdf

  7. J.   Shappir,  A.   Kolodny  and  Y.J.    Shacham-Diamand, "Diffusion  Profiling Using the Graded C-V Method,” IEEE Transactions on Electron Devices, Vol.  ED-27, p.993, 1980. pdf

  8. D.   Lubzens,  A.   Kolodny  and  Y.   Shacham,  "Automated  Measurement  and  Analysis  of MIS Interfaces in Narrow-Bandgap  Semiconductors,” IEEE Transactions on Electron Devices, Volume 28,  Issue 5,  pp. 546 – 551, 1981. pdf

  9. A.  Kolodny and I. Kidron,  "Two-dimensional  Effects  in  Intrinsinc Photo-Conductive Infrared  Detectors,”  Infrared  Physics, Vol.  22, pp.9-22, 1982. pdf

  10. B.  Eitan and A.  Kolodny, "Two  Components  of  Tunneling  Current  in  MOS  Structures,” Applied  Physics  Letters, Vol.  43, pp.106-108, 1983. pdf

  11. A. Kolodny,  S.   Nieh,  B.   Eitan  and  J. Shappir,  "Analysis  and  Modeling  of Floating-gate EEPROM Cells,” IEEE  Transactions on Electron Devices, Volume 33,  Issue 6,  pp. 835 – 844,  1986. pdf

  12. Y. Elboim, R. Ginosar and A. Kolodny, “A Clock Tuning Circuit for  System on Chip,”   IEEE Transactions on VLSI, vol. 11, pp.616-626, 2002. pdf  

  13. O. Milter and A. Kolodny, “Crosstalk Noise Reduction in Synthesized Digital  Logic Circuits,”  IEEE Transactions on VLSI , Volume: 11, pp. 1153 - 1158, Dec. 2003.  pdf

  14. E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, “QNoC: QoS architecture and  design process for cost-effective Network on Chip,”  Special issue on  Networks on Chip,  The Journal of Systems Architecture, Volume 50, pp. 105-128, February 2004. pdf

  15. E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny , “Cost considerations in Network on Chip" , Special issue on Networks on Chip, Integration - the  VLSI journal, Vol. 38, No. 1, pp. 19-42, Oct. 2004. pdf

  16. N. Dolev, A. Kornfeld and A. Kolodny, “Comparison of Sigma-Delta Converter Circuit Architectures in Digital CMOS Technology,”  Journal of Circuits, Systems and Computers, vol. 14, No. 3, pp.1-18, 2005. pdf

  17. T. Morad, U. Weiser, A. Kolodny, M. Valero and E. Ayguade,   “Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors,” IEEE Computer Architecture Letters, vol. 4,  2005. pdf

  18. M. Moreinis, A. Morgenshtein, I. Wagner and A. Kolodny, “Logic gates as  Repeaters,” IEEE Transactions on VLSI, Volume 14, pp.1276 - 1281, Nov. 2006.  pdf 

  19. S. Wimer, S. Michaely, K. Moiseev and A. Kolodny,  “Optimal Bus Sizing in  Migration of Processor Design,”  IEEE Transactions  on Circuits and Systems I, Volume 53,  Issue 5, pp. 1089 – 1100, May 2006. pdf

  20. M. Behar, A. Mendelson and A. Kolodny, “Trace Cache Sampling Filter,”  ACM Transactions on Computer Systems, 25, 1 (Feb. 2007), 3.  pdf

  21. Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, "Network Delays and Link Capacities in Application-Specific Wormhole NoCs," VLSI Design Special issue on Networks on Chip, 2007. pdf

  22. Z. Guz, I. Keidar, A. Kolodny and U. C. Weiser, "Nahalal: Memory Organization for Chip Multiprocessors", IEEE Computer architecture letters, June 2007. pdf

  23. K. Moiseev, S. Wimer and A. Kolodny, “On optimal ordering of signals in parallel wire bundles,” Integration – the VLSI Journal, Vol. 41, 2008, pp. 253 – 268. pdf

  24. M. Popovich, M. Sotman, A. Kolodny and E. G. Friedman, “Effective Radii of On-Chip Decoupling Capacitors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems , Vol. 16, No. 7, pp.894-907, July 2008. pdf

  25. M. Popovich, E. G. Friedman, M. Sotman and A. Kolodny, “On-Chip Power Distribution Grids with Multiple Supply Voltages for High Performance Integrated Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 7, pp.908-921, July 2008. pdf

  26. I. Walter, I. Cidon, and A. Kolodny, "BENoC - A Bus-Enhanced Network on-Chip for a Power Efficient CMP", IEEE Computer Architecture Letters, Volume 7, Issue 1, 2008. pdf

  27. K. Moiseev, A. Kolodny and S. Wimer, “Timing-Aware Power-Optimal Ordering of Signals,” ACM Transactions on Design Automation of Electronic Systems, Vol. 13, No. 4, Article 65, Sept. 2008. pdf

  28. R. Dobkin, R. Ginosar, and A. Kolodny, “QNoC Asynchronous Router," Integration , the VLSI Journal, Vol. 42, pp.103-115,
    February 2009. pdf

  29. K. Moiseev, A. Kolodny and S. Wimer, “Power-Delay Optimization in VLSI Microprocessors by Wire Spacing,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 14, Issue 4 (August 2009), Article No. 55, 2009, ISSN: 1084-4309. pdf

  30. Z. Guz, E. Bolotin, I. Keidar, A. Kolodny, A. Mendelson and U. Weiser, Many-Core vs. Many-Thread Machines: Stay Away From the Valley", IEEE Computer Architecture Letters, Volume 8,  Issue 1,  Jan. 2009. pdf

  31. A. Morgenshtein, E. G. Friedman, R. Ginosar and A. Kolodny, "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths with RC Interconnect," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008. pdf

  32. R. Dobkin, R. Ginosar, A. Kolodny and M. Moyal, "Asynchronous Current Mode Serial Communication," IEEE Transactions on VLSI systems, to appear in September 2010. pdf

  33.  K. Moiseev, A. Kolodny and S. Wimer, "Interconnect Bundle Sizing under Discrete Design Rules", accepted to IEEE Transactions on Computer Aided Design, 2010. pdf

  34. K. Moiseev, A. Kolodny and S. Wimer, "The Complexity of VLSI Power-Delay Optimization by Interconnect resizing", accepted to Journal of Combinatorial Optimization, 2010. pdf

  35. E. Krimer, M. Erez, I. Keslassy, A. Kolodny and I. Walter, "Static Timing Analysis for Modeling QoS in Networks on Chip", accepted to Journal of Parallel and Distributed Computing, 2010.

  36. P. Gelsinger, D. Kirkpatrick, A. Kolodny and G. Singer, "Such a CAD!," IEEE Solid-State Circuits Magazine, vol.2, no.3, pp.32-43, Summer 2010. pdf

  37. I. Vaisband, E. G. Friedman, R. Ginosar and A. Kolodny, "Low Power Clock Network Design,"  J. Low Power Electron. Appl. , 2010. pdf

  38. R. Manevich, I. Cidon, A. Kolodny, and W. Isask'har, "Centralized Adaptive Routing for NoCs," Computer Architecture Letters , vol.9, no.2, pp.57-60, Feb. 2010. pdf

  39. S. Wimer, K. Moiseev and A. Kolodny, "On VLSI Interconnect Optimization and Linear Ordering Problem", accepted to Optimization and Engineering, 2011. pdf

  40. Y. Aizik and A. Kolodny, "Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints," VLSI Design, 2011. pdf

  41. Evgeni Krimer, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter, Mattan Erez, “Static timing analysis for modeling QoS in networks-on-chip,”  J. Parallel Distrib. Comput. 71(5): 687-699 (2011).  pdf

  42. T.Y. Morad, A. Kolodny and U.C. Weiser, “Task Scheduling Based On Thread Essence and Resource Limitations,” accepted to Journal of Computers, Vol. 7, Issue 1, 2012. pdf

 

  Conference Proceedings

  1. A. Kolodny and J. Shappir, “Lateral effects in photodiodes,” Proceedings of ESSDRC, 1977; Also: IEEE Israel conference 1977.

  2. A.  Kolodny, R.  Friedman and  T.   Ben-Tzur,  "Rule-based Static  Debugger  and Simulation Compiler for VLSI Schematics,” Proceedings  of   1985   IEEE International   Conference   on  Computer-Aided Design (ICCAD), Santa Clara, CA, Nov.  1985.

  3. Y. Elboim, A. Kolodny, R. Ginosar,  “A Clock Tuning Circuit for IP Core Integration in SoC,” International workshop on IP-based synthesis and SoC  design,  Grenoble, France, Dec. 2000.

  4. Y. Elboim, A. Kolodny, R. Ginosar,  “A Clock Tuning Circuit for IP Core Integration in SoC,” Proc. DesigCon 2001, January 2001, Santa Clara, CA.

  5. O. Kosyakovsky, A.  Mendelson and A. Kolodny,. “The use of profile-based  trace classification for improving the power and performance of trace cache systems,” 4th Workshop on  Feedback-Directed and Dynamic Optimization  (FDDO-4), Austin, Texas, December 2001.  pdf

  6. Y. Elboim, R. Ginosar and A. Kolodny, “A Clock Tuning circuit for System on  Chip,” ACiD-WG 2002 Workshop, Munich, Germany, January 2002.

  7. O. Milter and A. Kolodny, “Crosstalk Delay Analysis and    Prevention Using  PrimeTime SI and Design Compiler in High  Frequency CPU Design,” Proc. SNUG, Boston, Mass., September 2002.

  8. Y. Elboim, R. Ginosar and A. Kolodny, “A Clock Tuning  Circuit for System on  Chip,” Proceedings of ESSCIRC 2002, Florence, Italy, September 2002. pdf

  9. A. Khamaisee, A. Mendelson and A. Kolodny, “Can hot traces help value prediction?,” 1st Value-prediction workshop,  San Diego, CA, June 2003. pdf

  10. A. Morgenshtein, M. Moreinis, I. Wagner and A. Kolodny, “Logic gates as Repeaters,” Proceedings of IFIP conference on VLSI-SoC , Darmstadt,  Germany, December 2003. pdf

  11. N. Magen, A. Kolodny, U. Weiser and N. Shamir,  “ Interconnect-power dissipation in a  Microprocessor,”  International System Level Interconnect   Prediction workshop (SLIP 2004), Paris, February 2004. pdf

  12. A. Morgenshtein, I. Cidon, A. Kolodny and R. Ginosar, “Comparative analysis of serial vs. parallel lings in NoC,”  Proceedings of 2004 International Symposium on System-on-Chip, pp. 185 – 188,  Tampere, Finland, November 2004. pdf

  13. M. Moreinis, A. Morgenshtein, I. A. Wagner and A.   Kolodny, “Repeater Insertion combined with LGR Methodology for on-Chip  Interconnect Timing Optimization,”  IEEE International Conference on  Electronics, Circuits and Systems, Tel Aviv, December 2004.  pdf

  14. S. Michaely, S.l Wimer, and A. Kolodny, “Optimal Resizing of Bus Wires in Layout Migration,” Proceedings of 11th IEEE International Conference on  Electronics, Circuits and Systems, Tel Aviv, December 2004. pdf

  15. A. Barger, D. Goren and A. Kolodny, “Design and Modeling   of Network on Chip Interconnects,” IEEE International Conference on Electronics, Circuits and Systems, Tel Aviv, December 2004. pdf

  16. E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, “Automatic and Hardware-Efficient SoC Integration by QoS Network on Chip,” IEEE International Conference on Electronics, Circuits and Systems, Tel Aviv, December 2004. pdf

  17. A. Morgenshtein, I. Cidon, A. Kolodny and R. Ginosar, “Micro-modem concept for communications in networks on chip,” IEEE International Conference on Electronics, Circuits and Systems, Tel Aviv, December 2004. pdf

  18. F. Chu, A. Kolodny, S. Maital and  D. Perlmutter,  “The innovation paradox:  Reconciling creativity & discipline - How winning organizations combine inspiration with perspiration,” Proceedings of IEEE International Engineering Management Conference, vol. 3 pp. 949-953, Singapore, October 2004. pdf

  19. A. Morgenshtein, I.Cidon, A. Kolodny and R. Ginosar, "Low-Leakage Repeaters for NoC Interconnects,” Proceedings of the IEEE International Symposium on Circuits and Systems 2005. pdf

  20. M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny, " On-Chip Power   Distribution  Grids with Multiple Supply Voltages for High Performance Integrated  Circuits,” Proceedings of the ACM Great Lakes Symposium on VLSI, pp. 2-7, April 2005  (received best student paper award for GLSVLSI 2005). pdf

  21. S. T. Morad, U. Weiser and A. Kolodny, “Why Not Data Trace Cache,”  Workshop on Duplicating, Deconstructing, and Debunking (WDDD, Held in conjunction with ISCA-32), 2005. pdf

  22. M. Behar, A. Mendelson and A. Kolodny, “Trace Cache Sampling Filter,” 14th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 255 – 266, 17-21 Sept. 2005. pdf

  23. M. Sotman, M..Popovich, A. Kolodny and E.G. Friedman, “Leveraging Symbiotic On-Die Decoupling Capacitance,” IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), October 2005. pdf

  24. K. Moiseev, S. Wimer and A. Kolodny, “Timing Optimization of Interconnect by Simultaneous Net-Ordering, Wire Sizing and Spacing,” Proceedings of the IEEE International Symposium on Circuits and Systems 2006. pdf

  25. I. Walter, Z. Guz, I. Cidon, R. Ginosar and A. Kolodny, “Efficient Link Capacity and QoS Design for Wormhole Network-on-Chip,” Proceedings of Design Automation and Test in Europe (DATE 2006). pdf

  26. R. Dobkin, R. Ginosar and A. Kolodny, " Fast Asynchronous Shift Register for Bit-Serial Communication," Proc. ASYNC 2006. pdf

  27. M. Sotman, A. Kolodny, M. Popovich and E. Friedman, "On-die Decoupling Capacitance: Frequency Domain Analysis of Activity Radius," Proceedings of the IEEE International Symposium on Circuits and Systems 2006. pdf

  28. M. Popovich, E.G. Friedman, M. Sotman, A. Kolodny and R.M. Secareanu, “Maximum effective distance of on chip Decoupling Capacitors in Power Distribution Grids,” Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 173 – 179, April/May 2006. pdf

  29. A. Barger, D. Goren and A. Kolodny, “Simple Criterion for Maximizing Data Rate in NoC Links”, 10th IEEE Workshop on Signal Propagation on Interconnects, Berlin, May 2006. (pdf)

  30. A. Morgenshtein, A. Kolodny, R. Ginosar, "Link Division Multiplexing forNoC Links", IEEE 24th Convention of Electrical and Electronics Engineers in Israel, Israel, pp. 245-249, November 2006. pdf

  31. A. Morgenshtein, A. Kolodny, R. Ginosar, "Asynchronous Bit-stream Compression. ",  IEEE 24th Convention of Electrical and Electronics Engineers in Israel, Israel, pp. 241-244, November 2006. pdf

  32. K. Moiseev, S. Wimer  and A. Kolodny, "An effective technique for simultaneous interconnect channel delay and noise reduction in nanometer VLSI design", IEEE 24th Convention of Electrical and Electronics Engineers in Israel, Israel, November 2006. pdf

  33. R. Dobkin, Y. Perelman, T. Liran, R. Ginosar and A. Kolodny, "High rate wave-pipelined asynchronous on-chip bit-serial data link", Accepted to ASYNC 2007.  pdf

  34. E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, "Routing Table Minimization for Irregular Mesh NoCs", DATE 2007,Nice, France, March 2007. pdf

  35. E. Bolotin, Z. Guz, I. Cidon, R. Ginosar and A. Kolodny, "The Power of Priority: NoC based Distributed Cache Coherency", NOCS 2007, Princeton, NJ, May 2007. pdf

  36. Walter, I. Cidon, R. Ginosar and A. Kolodny, "Access regulation to Hot-Modules in Wormhole Networks", NOCS 2007, Princeton, NJ, May 2007. pdf

  37. Dobkin, Y. Perelman, T. Liran, R. Ginosar, and A. Kolodny, “High rate wave-pipelined asynchronous on-chip bit-serial data link,” Thirteenth IEEE International Symposium on Asynchronous Circuits and Systems, Berkeley, USA, March 2007. pdf

  38. A. Morgenshtein, E. G. Friedman, R. Ginosar, and A. Kolodny, "Timing Optimization in Logic with Interconnect," Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, pp. 19 - 26, April 2008. ppt

  39. R. Dobkin, A. Morgenshtein, A. Kolodny, R. Ginosar, "Parallel vs. Serial On-Chip Communication," SLIP 2008, Newcastle, UK, April 2008. ppt

  40. Z. Guz, I. Keidar, A. Kolodny, and U. Weiser, "Utilizing Shared Data in Chip Multiprocessors with the Nahalal Architecture,"  20th ACM Symp. on Parallelism in Algorithms and Architectures (SPAA'08), special track on Hardware and Software Techniques to Improve the Programmability of Multicore Machines, June 2008. (SPAA Best Paper Award).   pdf  ppt

  41. K. Moiseev, A. Kolodny and S. Wimer, "Wire Spacing, Planar Graphs and the Minimization of Dynamic Power in VLSI Microprocessors," VLSI-SOC 2008. pdf

  42. I. Vaisband, E. Friedman, R. Ginosar and A. Kolodny, "Power Efficient Tree-Based Crosslinks for Skew Reduction," GLSVLSI 2009. pdf

  43. Y. Aizik and A. Kolodny, "Exploration of Energy-Delay Tradeoffs in Digital Circuit Design,"  IEEEI 2008. pdf

  44. R. Beraha, I. Walter, I. Cidon and A. Kolodny, "The Design of a Latency Constrained, Power Optimized NoC for a 4G SoC", NOCS 2009, San Diego, CA, May 2009.

  45. R. Manevich, I. Walter, I. Cidon and A. Kolodny, "Best of Both Worlds: A Bus-Enhanced NoC (BENoC)", NOCS 2009, San Diego, CA, May 2009. pdf

  46. E. Krimer, M. Erez, I. Keslassy, A. Kolodny and I. Walter, "Packet-Level Static Timing Analysis for NoCs", NOCS 2009, San Diego, CA, May 2009. pdf

  47. I. Walter, I. Cidon, and A. Kolodny, D. Sigalov, "The Era of Many-Modules SoC: Revisiting the NoC Mapping Problem", Second International Workshop on Network on Chip Architectures (NoCArc), 2010.

  48. Y. Ben-Itzhak, I. Cidon, and A. Kolodny, "Performance and Power Aware CMP Thread Allocation Modeling", International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2010), January 2010. pdf

  49. I. Walter, I. Cidon, and A. Kolodny, D. Sigalov, " Leveraging Application-Level Requirements in The Design of a NoC for a 4G SoC - a Case Study", DATE 2010. pdf

  50. S. Beer, R. Ginosar, R. and A. Kolodny, "The Devolution of Synchronizers", ASYNC 2010. pdf

  51. A. Abdel-hadi, E.G. Friedman, R. Ginosar and A. Kolodny, " Timing–Driven Variation–Aware Nonuniform Clock Mesh Synthesis," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 15 - 20, May 2010.  pdf

  52. Z. Guz, O. Itzhak, I. Kediar. A. Kolodny, A. Mendelson and U.C. Weiser, "Threads vs. Caches: Modeling the Behavior of Parallel Workloads", ICCD 2010.  pdf

  53. T. Morad, A.Kolodny and U.C. Weiser, "Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors", PAAP 2010. pdf

  54. R. Manevich, I. Cidon, A. Kolodny and I.Walter, "best of both worlds: A Bus Enhanced NoC", IEEEI 2010.

  55. S. Kvatinsky,   E. G. Friedman , A. Kolodny  and  L. Schächter, "Power Grid Analysis Based on a Macro Circuits Model", IEEEI 2010. pdf

  56. G. Sizikov, E.G. Friedman, A. Kolodny and M. Zelikson, Frequency Dependent Efficiency Model of On-Chip DC-DC Buck Converters", IEEEI 2010. pdf

  57. G. Sizikov, E.G. Friedman, A. Kolodny and M. Zelikson, "Efficiency Optimization of Integrated DC-DC Buck Converters," ICECS 2010. pdf

  58. T.Y. Morad, A. Kolodny and U.C. Weiser, “Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors,” PAAP 2010.  pdf

  59. Y. Ben-itzhak, I. Cidon and A. Kolodny, "Delay Analysis of Wormhole Based Heterogeneous NoC,"   NOCS 2011.  pdf

  60. S. Beer, R. Ginosar, M. Priel, R. Dobkin, A. Kolodny, “An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm”,  ISCAS 2011.  pdf

  61. Y. Ben-Itzhak, E. Zahavi, I. Cidon and A. Kolodny, “NoCs simulation framework for OMNeT++”, NOCS 2011. pdf

  62. S. Kvatinsky, E.G. Friedman, A. Kolodny and U. C. Weiser,”Memristor-based IMPLY Logic Design Procedure,” ICCD 2011. pdf

  63. R. Manevich, I.Cidon,A. Kolodny, I. Walter and S. Wimer, “Centralized Adaptive Routing for NoCs,” EUROMICRO Conference on Digital System Design - DSD 2011. pdf

  64. Y. Ben-Itzhak, E. Zahavi, I. Cidon and A. Kolodny, “HNOCS: Modular Open-Source Simulator for Heterogeneous NoCs,” submitted to DATE 2012.

     

     

 

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