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"Threads vs. Caches: Modeling the Behavior of Parallel Workloads",
Z. Guz, O. Itzhak, I. Keidar, A. Kolodny, A. Mendelson, and U. C. Weiser,
the 28th IEEE International Conference on Computer Design (ICCD'10), October 2010
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"Order is Power: Selective Packet Interleaving for Energy Efficient Networks-on-Chip",
A. Berman, R. Ginosar, and I. Keidar,
the 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC'10), September 2010
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"Mitigating Inter-Cell Coupling in MLC NAND Flash via Coding",
A. Berman, and Y. Birk,
the 5th Annual Flash Memory Summit (FMS'10), August 2010
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"On Maintaining Multiple Versions in STM",
D. Perelman, R. Fan, and I. Keidar
in the 29th ACM Symp. on Principles of Distributed Computing (PODC'10), pages 16-25, July 2010
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"Solid-State Drive (SSD) Future Architectures",
A. Berman, and Y. Birk,
the 5th Annual Symposium on Future Trends in Service-Oriented Computing (FutureSOC'10), June 2010
Video: link
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"Leveraging Application-Level Requirements in The Design of a NoC for a 4G SoC - a Case Study",
R. Beraha, I. Walter, I. Cidon, and A. Kolodny,
the Design, Automation and Test in Europe conference (DATE), 2010
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"SMV: Selective Multi-Versioning STM",
I. Keidar and D. Perelman,
the 5th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2010) , Paris, France, April 2010
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"Performance and Power Aware CMP Thread Allocation Modeling",
Y. Ben-Itzhak, I. Cidon, and A. Kolodny
International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2010), January 2010
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"Low Overhead Error Detection for Networks-on-Chip",
A. Berman, and I. Keidar,
the 27th IEEE International Conference on Computer Design (ICCD 09), October 2009
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"Multiple Clock and Voltage Domains for Chip Multi Processors",
E. Rotem, R. Ginosar, A. Mendelson and U. Weiser,
IEEE 42nd International Symposium on Microarchitecture (MICRO), New York, 2009
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"The Era of Many-Modules SoC: Revisiting the NoC Mapping Problem",
I. Walter, I. Cidon, A. Kolodny, and D. Sigalov
the Second International Workshop on Network on Chip Architectures (NoCArc), 2009
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"Modeling Tools for CMP Research",
Z. Guz and I. Walter,
the 4th Multi-Core Forum, June 2009
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"Reliable Architecture for Flash Memory",
A. Berman, and U. C. Weiser,
Workshop on Emerging Memory Technologies, 36th ACM/IEEE International Symposium on Computer Architecture (ISCA'09), June 2009
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"Transactifying Apache's Cache Module",
H. Eran, O. Lutzky, Z. Guz, and I. Keidar,
SYSTOR 2009 - The Israeli Experimental Systems Conference, May 2009
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"The Capacity Allocation Paradox",
A. Baron, R. Ginosar, and I. Keslassy,
IEEE Infocom '09, April 2009
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The Elements of NoC-A Tutorial (NOCS2009)
I. Cidon, A. Kolodny,and R. Ginosar
the ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), 2009
part1,
part2,
part3,
part4
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"Best of Both Worlds: A Bus Enhanced NoC (BENoC)",
R. Manevich, I. Walter, I. Cidon, and A. Kolodny,
the ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), 2009
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"Utilizing Shared Data in Chip Multiprocessors with the Nahalal Architecture",
Z. Guz, I. Keidar, A. Kolodny, and U. C. Weiser
20th ACM Symp. on Parallelism in Algorithms and Architectures (SPAA'08), Munich, Germany, June 2008
SPAA Best Paper Award
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"Statistical Approach to NoC Design",
I. Cohen, O. Rottenstreich, and I. Keslassy,
ACM/IEEE NoCS '08, Newcastle, UK, April 2008
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"Parallel vs. Serial On-Chip Communication",
R. Dobkin, A. Morgenshtein, A. Kolodny, and R. Ginosar,
ACM International Workshop on System Level Interconnect Prediction (SLIP), Newcastle, UK, April, 2008
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"Timing Optimization in Logic with Interconnect",
A. Morgenshtein, E. G. Friedman, R. Ginosar and A. Kolodny,
Invited Paper, ACM International Workshop on System Level Interconnect Prediction (SLIP), Newcastle, UK, April, 2008
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"NoC: Network OR Chip?",
I. Cidon,
Keynote talk, NOCS 2007
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"Access Regulation to Hot-Modules in Wormhole NoCs",
I. Walter, I. Cidon, R. Ginosar, A. Kolodny,
NOCS 2007
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"The Power of Priority: NoC based Distributed Cache Coherency",
E. Bolotin, Z. Guz, I. Cidon, R. Ginosar, A. Kolodny,
NOCS 2007
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"NoC-Based FPGA: Architecture and Routing",
R. Gindin, I. Cidon, and I. Keidar,
NOCS 2007
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"Routing Table Minimization for Irregular Mesh NoCs",
E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny,
DATE 2007
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"High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link",
R. Dobkin, Y. Perelman, T. Liran, R. Ginosar, A. Kolodny,
ASYNC 2007
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"Asynchronous Bit-stream Compression (ABC)",
A. Morgenshtein, A. Kolodny, R. Ginosar,
IEEE 24th Convention of Electrical and Electronics Engineers in Israel, pp. 241-244, November 2006
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"Link Division Multiplexing (LDM) for Network-on-Chip Links",
A. Morgenshtein, A. Kolodny, R. Ginosar,
IEEE 24th Convention of Electrical and Electronics Engineers in Israel, pp. 245-249, November 2006
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"Fast Asynchronous Shift Register for Bit-Serial Communication",
R. Dobkin, R. Ginosar, A. Kolodny,
ASYNC, 2006
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"Efficient Link Capacity and QoS Design for Wormhole Network-on-Chip",
Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny,
DATE, pp. 9-14, March 2006
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"Low-Leakage Repeaters for NoC Interconnects",
A. Morgenshtein, I. Cidon, A. Kolodny, R. Ginosar,
Special Session "Repeater Insertion for Nanometer Technologies - Timing is NOT Everything",
ISCAS, pp. 600-603, May 2005
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"Micro-Modem - Reliability Solution for NoC Communications",
A. Morgenshtein, E. Bolotin, I. Cidon, A. Kolodny, R. Ginosar,
ICECS, December 2004
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"Automatic Hardware-Efficient SoC Integration by QoS Network on Chip",
E. Bolotin, A. Morgenshtein, I. Cidon, A. Kolodny, R. Ginosar,
ICECS, December 2004
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"Network on Chip",
E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny,
Clubnet-Technion, December 2003