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"Performance and Power Aware CMP Thread Allocation Modeling",
Y. B. Itzhak, I. Cidon, and A. Kolodny
International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2010), January 2010
Paper: pdf
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"Low Overhead Error Detection for Networks-on-Chip",
A. Berman, and I. Keidar,
27th IEEE International Conference on Computer Design (ICCD 09), October 2009
Paper: pdf
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"On Avoiding Spare Aborts in Transactional Memory",
I. Keidar and D. Perelman,
21st ACM Symp. on Parallelism in Algorithms and Architectures (SPAA 09), Aug 2009
Paper: pdf
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"Packet-Level Static Timing Analysis for NoCs",
E. Krimer, I. Keslassy, A. Kolodny, I. Walter, and M. Erez,
Technical Report CCIT #737, Department of Electrical Engineering, Technion, July 2009
Paper: pdf
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"Reliable Architecture for Flash Memory",
A. Berman, and U. C. Weiser,
Workshop on Emerging Memory Technologies, 36th ACM/IEEE International Symposium on Computer Architecture (ISCA'09), June 2009
Paper: pdf
Talk: ppt
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"Many-Core vs. Many-Thread Machines: Stay Away From the Valley",
Z. Guz, E. Bolotin, I. Keidar, A. Kolodny, A. Mendelson, and U. C. Weiser,
IEEE Computer Architecture Letters, April 2009
Paper: pdf
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"The Capacity Allocation Paradox",
A. Baron, R. Ginosar, and I. Keslassy,
IEEE Infocom '09, April 2009
Paper: pdf
Talk: ppt
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"Best of Both Worlds: A Bus Enhanced NoC (BENoC)",
R. Manevich, I. Walter, I. Cidon, and A. Kolodny,
the ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), 2009
Paper: pdf
Talk: ppt
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"Transactifying Apache's Cache Module",
H. Eran, O. Lutzky, Z. Guz, and I. Keidar,
SYSTOR 2009 - The Israeli Experimental Systems Conference, May 2009
Paper: pdf
Talk: pdf
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"Multiple Multithreaded Applications on Asymmetric and Symmetric Chip MultiProcessors",
T. Y. Morad, A. Kolodny, and U. C. Weiser,
Technical Report CCIT 701 , Technion Department of Electrical Engineering, August 2008
Paper: pdf
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"BENoC - A Bus-Enhanced Network on-Chip for a Power Efficient CMP",
I. Walter, I. Cidon, and A. Kolodny,
IEEE Computer Architecture Letters, Volume 7, Issue 1, 2008
Paper: pdf
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"Utilizing Shared Data in Chip Multiprocessors with the Nahalal Architecture",
Z. Guz, I. Keidar, A. Kolodny, and U. C. Weiser
20th ACM Symp. on Parallelism in Algorithms and Architectures (SPAA'08), Munich, Germany, June 2008
SPAA Best Paper Award
Paper: pdf
Talk: ppt
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"Statistical Approach to NoC Design",
I. Cohen, O. Rottenstreich, and I. Keslassy,
ACM/IEEE NoCS '08, Newcastle, UK, April 2008
Paper: pdf
Talk: ppt
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"Parallel vs. Serial On-Chip Communication",
R. Dobkin, A. Morgenshtein, A. Kolodny, and R. Ginosar,
ACM International Workshop on System Level Interconnect Prediction (SLIP), Newcastle, UK, April, 2008
Paper: pdf
Talk: pdf
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"Timing Optimization in Logic with Interconnect",
A. Morgenshtein, E. G. Friedman, R. Ginosar and A. Kolodny,
Invited Paper, ACM International Workshop on System Level Interconnect Prediction (SLIP), Newcastle, UK, April, 2008
Paper: pdf
Talk: ppt
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"BENoC: Bus-Enhanced Network on-Chip",
I. Walter, I. Cidon, and A. Kolodny,
Technical Report CCIT #677, Department of Electrical Engineering, Technion, December 2007
Paper: pdf
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"Nahalal: Cache Organization for Chip Multiprocessors",
Z. Guz, I. Keidar, A. Kolodny, U. C. Weiser,
IEEE Computer Architecture Letters, vol. 6, no. 1, May 2007
Paper: pdf
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"Access Regulation to Hot-Modules in Wormhole NoCs",
I. Walter, I. Cidon, R. Ginosar, A. Kolodny,
NOCS 2007
Paper: pdf
Talk: ppt
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"The Power of Priority: NoC based Distributed Cache Coherency",
E. Bolotin, Z. Guz, I. Cidon, R. Ginosar, A. Kolodny,
NOCS 2007
Paper: pdf
Talk: ppt
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"NoC-Based FPGA: Architecture and Routing",
R. Gindin, I. Cidon, and I. Keidar,
NOCS 2007
Paper: pdf
Talk: ppt
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"Network Delays and Link Capacities in Application-Specific Wormhole NoCs",
Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny,
VLSI Design, vol. 2007, Article ID 90941, May 2007
Paper: pdf
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"Routing Table Minimization for Irregular Mesh NoCs",
E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny,
DATE 2007
Paper: pdf
Talk: ppt
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"High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link",
R. Dobkin, Y. Perelman, T. Liran, R. Ginosar, A. Kolodny,
ASYNC 2007
Paper: pdf
Talk: ppt
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"Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths with RC Interconnect",
A. Morgenshtein, E.G. Friedman, R. Ginosar, A. Kolodny,
Technical Report CCIT 612, Technion Department of Electrical Engineering, January 2007
Paper: pdf
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"Nahalal: Memory Organization for Chip Multiprocessors",
Z. Guz, I. Keidar, A. Kolodny, U. C. Weiser,
Technical Report CCIT 600, Technion Department of Electrical Engineering, September 2006
Paper: pdf
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"Architecture and Routing in NOC Based FPGAs",
R. Gindin, I. Cidon and I. Keidar,
Technical Report CCIT , Technion Department of Electrical Engineering, 2006
Paper: pdf
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"Link Division Multiplexing (LDM) for Network-on-Chip Links",
A. Morgenshtein, A. Kolodny, R. Ginosar,
IEEE 24th Convention of Electrical and Electronics Engineers in Israel, pp. 245-249, November 2006
Paper: pdf
Talk: ppt
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"Asynchronous Bit-stream Compression (ABC)",
A. Morgenshtein, A. Kolodny, R. Ginosar,
IEEE 24th Convention of Electrical and Electronics Engineers in Israel, pp. 241-244, November 2006
Paper: pdf
Talk: ppt
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"High-Speed Serial Interconnect for NoC",
R. Dobkin, R. Ginosar, A. Kolodny,
NoC Workshop, DATE'06, 2006.
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"Efficient Link Capacity and QoS Design for Wormhole Network-on-Chip",
Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny,
DATE, pp. 9-14, March 2006
Paper: pdf
Talk: ppt
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"Fast Asynchronous Shift Register for Bit-Serial Communication",
R. Dobkin, R. Ginosar and A. Kolodny,
ASYNC 2006
Paper: pdf
Talk: pdf
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"Efficient Routing in Irregular Topology NoCs",
E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny,
Technical Report CCIT #554 , Technion Department of Electrical Engineering, September 2005
Paper: pdf
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"Curing Hotspots in Wormhole NoCs",
I. Walter, I. Cidon, R. Ginosar and A. Kolodny,
CCIT Report 568, Technion Department of Electrical Engineering, EE Pub No. 1520, December 2005
Paper: pdf
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"Zooming in on Network-on-Chip Architectures",
I. Cidon and I. Keidar,
Technical Report CCIT 565, Technion Department of Electrical Engineering, December 2005
Paper: pdf
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"Trace Cache Sampling Filter",
M. Behar, A. Mendelson, A. Kolodny,
PACT 2005
Paper: pdf
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"Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors",
T. Y. Morad, U. C. Weiser, A. Kolodny, M. Valero, E. Ayguadé,
Computer Architecture Letters, vol. 4, July 2005
Paper: pdf
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"Low-Leakage Repeaters for NoC Interconnects",
A. Morgenshtein, I. Cidon, A. Kolodny, R. Ginosar,
Special Session "Repeater Insertion for Nanometer Technologies - Timing is NOT Everything",
ISCAS, pp. 600-603, May 2005
Paper: pdf
Talk: ppt
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"An Asynchronous Router for Multiple Service Levels Networks on Chip",
R. Dobkin, V. Vishnyakov, E. Friedman and R.Ginosar,
ASYNC, pp.44-53, 2005
Paper: pdf
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"Fast Asynchronous Bit-Serial Interconnects for Network-on-Chip",
R. Dobkin, I.Cidon, R.Ginosar, A.Kolodny and A.Morgenshtein,
CCIT Technical Report 529, 2004
Paper: pdf
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"Data Synchronization Issues in GALS SoCs",
R. Dobkin, R. Ginosar and C. Sotiriou,
ASYNC, pp. 170-179, 2004
Paper: pdf
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"Micro-Modem - Reliability Solution For NoC Communications",
A. Morgenshtein, E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny,
ICECS, 2004
Paper: pdf
Talk:ppt
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"Automatic Hardware-Efficient SoC Integration by QoS Network on Chip",
E. Bolotin, A. Morgenshtein, I. Cidon, R. Ginosar, A. Kolodny,
ICECS, 2004
Paper: pdf
Talk: ppt
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"Comparative Analysis of Serial vs. Parallel Links in Networks on Chip",
A. Morgenshtein, I. Cidon, A. Kolodny, R. Ginosar,
SoC, 2004
Paper: pdf
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"QNoC: QoS architecture and design process for Network on Chip",
E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny,
Special issue on Networks on Chip, The Journal of Systems Architecture, December 2003
Paper: pdf
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"Cost considerations in Network on Chip",
E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny,
Special issue on Networks on Chip, Integration - The VLSI Journal, 2003
Paper: pdf