• "Centralized Adaptive Routing for NoCs",
    R. Manevich, I. Cidon, A. Kolodny, and I. Walter,
    to appear in IEEE Computer Architecture Letters
  • "Static Timing Analysis for Modeling QoS in Networks on Chip",
    E. Krimer, I. Keslassy, A. Kolodny, I. Walter, and M. Erez,
    to appear in the Journal of Parallel and Distributed Computing
  • "Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors",
    T. Y. Morad, A. Kolodny, and U. C. Weiser,
    to appear in the 3rd International Symposium on Parallel Architectures, Algorithms and Programming (PAAP'10), December 2010
  • "Integrating De-Duplication and Write for Increased Endurance and Performance of Solid-State Drives",
    A. Berman, and Y. Birk,
    to appear in 26th IEEE Convention of Electrical and Electronics Engineers in Israel (IEEEI'10), November 2010
  • "Threads vs. Caches: Modeling the Behavior of Parallel Workloads",
    Z. Guz, O. Itzhak, I. Keidar, A. Kolodny, A. Mendelson, and U. C. Weiser,
    the 28th IEEE International Conference on Computer Design (ICCD'10), October 2010
    Paper: pdf
    Talk: pptx
  • "Order is Power: Selective Packet Interleaving for Energy Efficient Networks-on-Chip",
    A. Berman, R. Ginosar, and I. Keidar,
    the 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC'10), September 2010
    Paper: pdf
    Talk: pdf
  • "On Maintaining Multiple Versions in STM",
    D. Perelman, R. Fan, and I. Keidar
    in the 29th ACM Symp. on Principles of Distributed Computing (PODC'10), pages 16-25, July 2010
    Paper: pdf
    Talk: pptx
  • "Statistical Approach to Networks-on-Chip",
    I. Cohen, O. Rottenstreich, and I. Keslassy,
    IEEE Transactions on Computers, Vol. 59, No. 6, pp. 748-761, June 2010
    Paper: pdf
  • "Leveraging Application-Level Requirements in The Design of a NoC for a 4G SoC - a Case Study",
    R. Beraha, I. Walter, I. Cidon, and A. Kolodny,
    the Design, Automation and Test in Europe conference (DATE), 2010
    Paper: pdf
    Talk: pptx
  • "SMV: Selective Multi-Versioning STM",
    I. Keidar and D. Perelman,
    the 5th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2010) , Paris, France, April 2010
    Paper: pdf
    Talk: pptx
  • "Performance and Power Aware CMP Thread Allocation Modeling",
    Y. Ben-Itzhak, I. Cidon, and A. Kolodny
    International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2010), January 2010
    Paper: pdf
    Talk: pptx