By Year:

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

By Topic:

Software

Architecture

Networking

Physical Layer

Asynchronous

Software

• SMV: Selective Multi-Versioning STM.
  D. Perelman, A. Byshevsky, O. Litmanovich, and I. Keidar
  To appear in the 25th Int'l Symp. on Distributed Computing (DISC'11), Rome, Italy, September 2011.
  Full version: Tech. Rep. CCIT 781, Technion EE, Jan 2011. (Preliminary version in TRANSACT'10, April 2010.)
  TRANSACT Talk slides: pptx, pdf.
  
  
• Scalable Producer-Consumer Task Pools with Adjustable Fairness and Contention.
  D. Basin, R. Fan, I. Keidar, O. Kiselov, and D. Perelman
  To appear in the 25th Int'l Symp. on Distributed Computing (DISC'11), Rome, Italy, September 2011.
  
  
• LiMoSense - Live Monitoring in Dynamic Sensor Networks .
  I. Eyal, I. Keidar, and R. Rom
  To appear in the 7th Int'l Symp. on Algorithms for Sensor Systems, Wireless Ad Hoc Networks and Autonomous Mobile Entities (ALGOSENSORS'11), Saarbruecken, Germany, September 2011.
  Full version: Tech. Rep. CCIT 786, Technion EE, 2011.
  
  
• Dynamic Atomic Storage Without Consensus.
  M. Aguilera, I. Keidar, D. Malkhi, and A. Shraer:
  In Journal of the ACM (JACM), 58:2, Apr 2011. (Previous version in PODC'09.)
  pdf (PODC version), pdf (TR version), ppt.
  
  
• Fail-Aware Untrusted Storage.
  C. Cachin, I. Keidar, and A. Shraer
  In SIAM Journal on Computing (SICOMP) 40:2, pages 493-533, Apr 2011. (Previous version in DSN'09.)
  pdf (DSN version), pdf (full version), ppt.
  
  
• Tolerant Value Speculation in Coarse-Grain Streaming Computations.
  N. Azuelos, I. Keidar, and A. Zaks
  In the 25th IEEE Int'l Parallel and Distributed Processing Symp. (IPDPS'11), pages 490-501, Anchorage, Alaska, May 2011.
  
  
• A Shared File System Abstraction for Heterogeneous Architectures.
  M. Silberstein and I. Keidar
  Tech. Rep. CCIT 782, Technion EE, Jan 2011.
  
• "On Maintaining Multiple Versions in STM",
  D. Perelman, R. Fan, and I. Keidar
  in the 29th ACM Symp. on Principles of Distributed Computing (PODC'10), pages 16-25, July 2010
  Paper: pdf
  Talk: pptx
• "SMV: Selective Multi-Versioning STM",
  I. Keidar and D. Perelman,
  the 5th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2010) , Paris, France, April 2010
  Paper: pdf
  Talk: pptx
• "On Avoiding Spare Aborts in Transactional Memory",
  I. Keidar and D. Perelman,
  21st ACM Symp. on Parallelism in Algorithms and Architectures (SPAA 09), Aug 2009
  Paper: pdf
• "Transactifying Apache's Cache Module",
  H. Eran, O. Lutzky, Z. Guz, and I. Keidar,
  SYSTOR 2009 - The Israeli Experimental Systems Conference, May 2009
  Paper: pdf
  Talk: pdf

Architecture

• Multi-Amdahl: How Should I Divide My Heterogeneous Chip?.
  Tsahee Zidenberg, Isaac Keslassy, Uri Weiser
  IEEE Computer Architecture Letters
  IEEE computer Society Digital Library. IEEE Computer Society March 21 2012
  
• "Multi-Amdahl: Optimal Resource Sharing with Multiple Program Execution Segments,"
  Tsahee Zidenberg, Isaac Keslassy and Uri Weiser,
  Technical Report TR11-03, Comnet, Technion, Israel.
  Paper: pdf
  
• "A Four-Stage Mesochronous Synchronizer with Back-Pressure and Buffering for Short and Long Range Communications,"
  D. Verbitsky, R. Dobkin and R.Ginosar,
  Tech. Rep., 2011.
  Paper: pdf
  
• "Low Power Clock Network Design"
  I. Vaisband, E.G. Friedman, R. Ginosar and A. Kolodny,
  J. Low Power Electron. Appl. 2011, 1(1), 219-246;
  Paper: pdf
  
• "Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors",
  T. Y. Morad, A. Kolodny, and U. C. Weiser,
  to appear in the 3rd International Symposium on Parallel Architectures, Algorithms and Programming (PAAP'10), December 2010
  
• "Integrating De-Duplication and Write for Increased Endurance and Performance of Solid-State Drives",
  A. Berman, and Y. Birk,
  to appear in 26th IEEE Convention of Electrical and Electronics Engineers in Israel (IEEEI'10), November 2010
  
• "Threads vs. Caches: Modeling the Behavior of Parallel Workloads",
  Z. Guz, O. Itzhak, I. Keidar, A. Kolodny, A. Mendelson, and U. C. Weiser,
  the 28th IEEE International Conference on Computer Design (ICCD'10), October 2010
  Paper: pdf
  Talk: pptx
• "Performance and Power Aware CMP Thread Allocation Modeling",
  Y. B-Itzhak, I. Cidon, and A. Kolodny
  International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2010), January 2010
  Paper: pdf
  Talk: pptx
• "Multiple Clock and Voltage Domains for Chip Multi Processors",
  E. Rotem, R. Ginosar, A. Mendelson and U. Weiser,
  IEEE 42nd International Symposium on Microarchitecture (MICRO), New York, 2009
  Paper: pdf
  Talk: pptx
• "Reliable Architecture for Flash Memory",
  A. Berman, and U. C. Weiser,
  Workshop on Emerging Memory Technologies, 36th ACM/IEEE International Symposium on Computer Architecture (ISCA'09), June 2009
  Paper: pdf
  Talk: ppt
• "Many-Core vs. Many-Thread Machines: Stay Away From the Valley",
  Z. Guz, E. Bolotin, I. Keidar, A. Kolodny, A. Mendelson, and U. C. Weiser,
  IEEE Computer Architecture Letters, April 2009
  Paper: pdf
• "Multiple Multithreaded Applications on Asymmetric and Symmetric Chip MultiProcessors",
  T. Y. Morad, A. Kolodny, and U. C. Weiser,
  Technical Report CCIT 701 , Technion Department of Electrical Engineering, August 2008
  Paper: pdf
• "Utilizing Shared Data in Chip Multiprocessors with the Nahalal Architecture",
  Z. Guz, I. Keidar, A. Kolodny, and U. C. Weiser
  20th ACM Symp. on Parallelism in Algorithms and Architectures (SPAA'08), Munich, Germany, June 2008
  SPAA Best Paper Award
  Paper: pdf
  Talk: ppt
• "Nahalal: Cache Organization for Chip Multiprocessors",
  Z. Guz, I. Keidar, A. Kolodny, U. C. Weiser,
  IEEE Computer Architecture Letters, vol. 6, no. 1, May 2007
  Paper: pdf
• "Nahalal: Memory Organization for Chip Multiprocessors",
  Z. Guz, I. Keidar, A. Kolodny, U. C. Weiser,
  Technical Report CCIT 600, Technion Department of Electrical Engineering, September 2006
  Paper: pdf
• "Trace Cache Sampling Filter",
  M. Behar, A. Mendelson, A. Kolodny,
  PACT 2005
  Paper: pdf
• "Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors",
  T. Y. Morad, U. C. Weiser, A. Kolodny, M. Valero, E. Ayguadé,
  Computer Architecture Letters, vol. 4, July 2005
  Paper: pdf
• "Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors",
  T. Y. Morad, U. C. Weiser, A. Kolodny, M. Valero, E. Ayguadé,
  Technical Report CCIT 514 , Technion Department of Electrical Engineering, January 2005
  Paper: pdf

Networking

• "Centralized Adaptive Routing for NoCs",
  R. Manevich, I. Cidon, A. Kolodny, and I. Walter,
  to appear in IEEE Computer Architecture Letters
  
• "Static Timing Analysis for Modeling QoS in Networks on Chip",
  E. Krimer, I. Keslassy, A. Kolodny, I. Walter, and M. Erez,
  to appear in the Journal of Parallel and Distributed Computing
  
• "Order is Power: Selective Packet Interleaving for Energy Efficient Networks-on-Chip",
  A. Berman, R. Ginosar, and I. Keidar,
  the 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC'10), September 2010
  Paper: pdf
  Talk: pdf
• "Statistical Approach to Networks-on-Chip",
  I. Cohen, O. Rottenstreich, and I. Keslassy,
  IEEE Transactions on Computers, Vol. 59, No. 6, pp. 748-761, June 2010
  Paper: pdf
• "Leveraging Application-Level Requirements in The Design of a NoC for a 4G SoC - a Case Study",
  R. Beraha, I. Walter, I. Cidon, and A. Kolodny,
  the Design, Automation and Test in Europe conference (DATE), 2010
  Paper: pdf
  Talk: pptx
• "The Era of Many-Modules SoC: Revisiting the NoC Mapping Problem",
  I. Walter, I. Cidon, A. Kolodny, and D. Sigalov
  the Second International Workshop on Network on Chip Architectures (NoCArc), 2009
  Paper: pdf
  Talk: pptx
• "Low Overhead Error Detection for Networks-on-Chip",
  A. Berman, and I. Keidar,
  the 27th IEEE International Conference on Computer Design (ICCD 09), October 2009
  Paper: pdf
  Talk: pdf
• "Packet-Level Static Timing Analysis for NoCs",
  E. Krimer, I. Keslassy, A. Kolodny, I. Walter, and M. Erez,
  Technical Report CCIT #737, Department of Electrical Engineering, Technion, July 2009
  Paper: pdf
• "The Capacity Allocation Paradox",
  A. Baron, R. Ginosar, and I. Keslassy,
  IEEE Infocom '09, April 2009
  Paper: pdf
  Talk: ppt
• "Best of Both Worlds: A Bus Enhanced NoC (BENoC)",
  R. Manevich, I. Walter, I. Cidon, and A. Kolodny,
  the ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS), 2009
  Paper: pdf
  Talk: ppt
• "BENoC - A Bus-Enhanced Network on-Chip for a Power Efficient CMP",
  I. Walter, I. Cidon, and A. Kolodny,
  IEEE Computer Architecture Letters, Volume 7, Issue 1, 2008
  Paper: pdf
• "Statistical Approach to NoC Design",
  I. Cohen, O. Rottenstreich, and I. Keslassy,
  ACM/IEEE NoCS '08, Newcastle, UK, April 2008
  Paper: pdf
  Talk: ppt
• "BENoC: Bus-Enhanced Network on-Chip",
  I. Walter, I. Cidon, and A. Kolodny,
  Technical Report CCIT #677, Department of Electrical Engineering, Technion, December 2007
  Paper: pdf
• "Access Regulation to Hot-Modules in Wormhole NoCs",
  I. Walter, I. Cidon, R. Ginosar, A. Kolodny,
  NOCS 2007
  Paper: pdf
  Talk: ppt
• "The Power of Priority: NoC based Distributed Cache Coherency",
  E. Bolotin, Z. Guz, I. Cidon, R. Ginosar, A. Kolodny,
  NOCS 2007
  Paper: pdf
  Talk: ppt
• "NoC-Based FPGA: Architecture and Routing",
  R. Gindin, I. Cidon, and I. Keidar,
  NOCS 2007
  Paper: pdf
  Talk: ppt
• "Network Delays and Link Capacities in Application-Specific Wormhole NoCs",
  Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny,
  VLSI Design, vol. 2007, Article ID 90941, May 2007
  Paper: pdf
• "Routing Table Minimization for Irregular Mesh NoCs",
  E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny,
  DATE 2007
  Paper: pdf
  Talk: ppt
• "Architecture and Routing in NOC Based FPGAs",
  R. Gindin, I. Cidon and I. Keidar,
  Technical Report CCIT , Technion Department of Electrical Engineering, 2006
  Paper: pdf
• "Efficient Link Capacity and QoS Design for Wormhole Network-on-Chip",
  Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny,
  DATE, pp. 9-14, March 2006
  Paper: pdf
  Talk: ppt
• "Architecture and Routing in NOC Based FPGAs",
  R. Gindin, I. Cidon and I. Keidar,
  Technical Report CCIT , Technion Department of Electrical Engineering, 2006
  Paper: pdf
• "Curing Hotspots in Wormhole NoCs",
  I. Walter, I. Cidon, R. Ginosar and A. Kolodny,
  CCIT Report 568, Technion Department of Electrical Engineering, EE Pub No. 1520, December 2005
  Paper: pdf
• "Zooming in on Network-on-Chip Architectures",
  I. Cidon and I. Keidar,
  Technical Report CCIT 565, Technion Department of Electrical Engineering, December 2005
  Paper: pdf
• "Automatic Hardware-Efficient SoC Integration by QoS Network on Chip",
  E. Bolotin, A. Morgenshtein, I. Cidon, R. Ginosar, A. Kolodny,
  ICECS, 2004
  Paper: pdf
  Talk: ppt
• "QNoC: QoS architecture and design process for Network on Chip",
  E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny,
  Special issue on Networks on Chip, The Journal of Systems Architecture, December 2003
  Paper: pdf
• "Cost considerations in Network on Chip",
  E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny,
  Special issue on Networks on Chip, Integration - The VLSI Journal, 2003
  Paper: pdf

Physical Layer

• "Parallel vs. Serial On-Chip Communication",
  R. Dobkin, A. Morgenshtein, A. Kolodny, and R. Ginosar,
  ACM International Workshop on System Level Interconnect Prediction (SLIP), Newcastle, UK, April, 2008
  Paper: pdf
  Talk: pdf
• "Timing Optimization in Logic with Interconnect",
  A. Morgenshtein, E. G. Friedman, R. Ginosar and A. Kolodny,
  Invited Paper, ACM International Workshop on System Level Interconnect Prediction (SLIP), Newcastle, UK, April, 2008
  Paper: pdf
  Talk: ppt
• "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths with RC Interconnect",
  A. Morgenshtein, E.G. Friedman, R. Ginosar, A. Kolodny,
  Technical Report CCIT 612, Technion Department of Electrical Engineering, January 2007
  Paper: pdf
• "Link Division Multiplexing (LDM) for Network-on-Chip Links",
  A. Morgenshtein, A. Kolodny, R. Ginosar,
  IEEE 24th Convention of Electrical and Electronics Engineers in Israel, pp. 245-249, November 2006
  Paper: pdf
  Talk: ppt
• "Low-Leakage Repeaters for NoC Interconnects",
  A. Morgenshtein, I. Cidon, A. Kolodny, R. Ginosar,
  Special Session "Repeater Insertion for Nanometer Technologies - Timing is NOT Everything",
  ISCAS, pp. 600-603, May 2005
  Paper: pdf
  Talk: ppt
• "Micro-Modem - Reliability Solution For NoC Communications",
  A. Morgenshtein, E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny,
  ICECS, 2004
  Paper: pdf
  Talk: ppt
• "Comparative Analysis of Serial vs. Parallel Links in Networks on Chip",
  A. Morgenshtein, I. Cidon, A. Kolodny, R. Ginosar,
  SoC, 2004
  Paper: pdf

Asynchronous

• "Metastability and Synchronizers: A Tutorial,"
  R. Ginosar,
  to be published, IEEE Design & Test, Sept/Oct. 2011.
  Paper: pdf
  
• "High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link",
  R. Dobkin, Y. Perelman, T. Liran, R. Ginosar, A. Kolodny,
  ASYNC 2007
  Paper: pdf
  Talk: ppt
• "Asynchronous Bit-stream Compression (ABC)",
  A. Morgenshtein, A. Kolodny, R. Ginosar,
  IEEE 24th Convention of Electrical and Electronics Engineers in Israel, pp. 241-244, November 2006
  Paper: pdf
  Talk: ppt
• "High-Speed Serial Interconnect for NoC",
  R. Dobkin, R. Ginosar, A. Kolodny,
  NoC Workshop, DATE'06, 2006.
• "Fast Asynchronous Shift Register for Bit-Serial Communication",
  R. Dobkin, R. Ginosar and A. Kolodny,
  ASYNC 2006
  Paper: pdf
  Talk: pdf
• "An Asynchronous Router for Multiple Service Levels Networks on Chip",
  R. Dobkin, V. Vishnyakov, E. Friedman and R.Ginosar,
  ASYNC, pp.44-53, 2005
  Paper: pdf
• "Fast Asynchronous Bit-Serial Interconnects for Network-on-Chip",
  R. Dobkin, I.Cidon, R.Ginosar, A.Kolodny and A.Morgenshtein,
  CCIT Technical Report 529, 2004
  Paper: pdf
• "Data Synchronization Issues in GALS SoCs",
  R. Dobkin, R. Ginosar and C. Sotiriou,
  ASYNC, pp. 170-179, 2004
  Paper: pdf