Modern integrated systems in silicon employ multiple processors (often heterogeneous, a.k.a. asymmetric cores). On-chip communication plays a central role in the architecture of such systems. The communication mechanisms must satisfy different latency and bandwidth requirements for different signals and data flows, within constrained power and area costs. Access to distributed shared memories can become a major bottleneck.
Our vision of future nanoscale integrated systems involves many processors and shared memories, interconnected by on-chip packet-switched networks. We believe it is important to tackle these challenges by an interdisciplinary team of researchers, with diverse expertise in areas such as circuits, microarchitecture, VLSI, networking and concurrent programming. The MATRICS research group addresses several aspects of such systems, including:
- Networks on Chips (architecture and circuits, quality of service, routers)
- Chip Multi-Processor (CMP) architecture
- Shared memory architectures for CMP systems
- Advanced NoC services for CMP systems
- Software issues in CMP systems
The group also hosts the Israeli Ministry of Science Knowledge Center on ChipMultiprocessors (CMP).